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1. (WO2015047337) APPARATUS AND METHOD TO OPTIMIZE STT-MRAM SIZE AND WRITE ERROR RATE

Pub. No.:    WO/2015/047337    International Application No.:    PCT/US2013/062421
Publication Date: Fri Apr 03 01:59:59 CEST 2015 International Filing Date: Sat Sep 28 01:59:59 CEST 2013
IPC: G11C 11/15
Applicants: INTEL CORPORATION
Inventors: MANIPATRUNI, Sasikanth
NIKONOV, Dmitri E.
YOUNG, Ian A.
Title: APPARATUS AND METHOD TO OPTIMIZE STT-MRAM SIZE AND WRITE ERROR RATE
Abstract:
Described is an apparatus comprising: a first select-line; a second select-line; a bit-line; a first bit-cell including a resistive memory element and a transistor, the first bit-cell coupled to the first select-line and the bit-line; a buffer with an input coupled to the first select-line and an output coupled to the second select-line; and a second bit-cell including a resistive memory element and a transistor, the second bit-cell coupled to the second select-line and the bit-line. Described is a magnetic random access memory (MRAM) comprising: a plurality of rows, each row including: a plurality of bit-cells, each bit-cell having an MTJ device coupled to a transistor; and a plurality of buffers, each of which to buffer a select-line signal for a group of bit-cells among the plurality of bit-cells; and a plurality of bit-lines, each row sharing a single bit-line among the plurality of bit-cells in that row.