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1. (WO2015047318) SUBTRACTIVE SELF-ALIGNED VIA AND PLUG PATTERNING FOR BACK END OF LINE (BEOL) INTERCONNECTS
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2015/047318 International Application No.: PCT/US2013/062319
Publication Date: 02.04.2015 International Filing Date: 27.09.2013
IPC:
H01L 21/3205 (2006.01) ,H01L 21/28 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard MS: RNB-4-150 Santa Clara, California 95054, US
Inventors:
BRISTOL, Robert L.; US
GSTREIN, Florian; US
SCHENKER, Richard E.; US
NYHUS, Paul A.; US
WALLACE, Charles H.; US
YOO, Hui Jae; US
Agent:
BRASK, Justin K.; Blakely, Sokoloff, Taylor & Zafman LLP 1279 Oakmead Parkway Sunnyvale, California 94085-4040, US
Priority Data:
Title (EN) SUBTRACTIVE SELF-ALIGNED VIA AND PLUG PATTERNING FOR BACK END OF LINE (BEOL) INTERCONNECTS
(FR) MODÉLISATION DE TROU D'INTERCONNEXION ET DE FICHE AUTO-ALIGNÉE SOUSTRACTIVE POUR DES INTERCONNEXIONS D’EXTRÉMITÉ ARRIÈRE DE LIGNE (BEOL)
Abstract:
(EN) Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The interconnect structure further includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. The metal lines of the first grating are spaced apart from the metal lines of the second grating.
(FR) L’invention porte sur une modélisation de trou d'interconnexion et de fiche auto-alignée soustractive pour des interconnexions d’extrémité arrière de ligne (BEOL). Selon un exemple, une structure d’interconnexion pour un circuit intégré comprend une première couche de la structure d’interconnexion disposée au-dessus d’un substrat. La première couche comprend un premier réseau de lignes métalliques et de lignes de diélectrique alternées dans une première direction. Les lignes de diélectrique possèdent une surface la plus haute supérieure à une surface la plus haute des lignes métalliques. La structure d’interconnexion comprend en outre une seconde couche de la structure d’interconnexion disposée au-dessus de la première couche de la structure d’interconnexion. La seconde couche comprend un second réseau de lignes métalliques et de lignes de diélectrique alternées dans une seconde direction, perpendiculaire à la première direction. Les lignes de diélectrique possèdent une surface la plus basse inférieure à une surface la plus basse des lignes métalliques. Les lignes de diélectrique du second réseau chevauchent et sont en contact avec les lignes de diélectrique du premier réseau mais sont distinctes de ces dernières. Les lignes métalliques du premier réseau sont espacées des lignes métalliques du second réseau.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)