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1. (WO2015047314) TECHNIQUES TO COMPOSE MEMORY RESOURCES ACROSS DEVICES
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2015/047314 International Application No.: PCT/US2013/062310
Publication Date: 02.04.2015 International Filing Date: 27.09.2013
IPC:
G06F 13/14 (2006.01) ,G06F 12/00 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14
Handling requests for interconnection or transfer
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
Applicants:
ABOU GAZALA, Neven M. [EG/US]; US (US)
DIEFENBAUGH, Paul S. [US/US]; US (US)
JEGANATHAN, Nithyananda S. [IN/US]; US (US)
GORBATOV, Eugene [US/US]; US (US)
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US (AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BE, BF, BG, BH, BJ, BN, BR, BW, BY, BZ, CA, CF, CG, CH, CI, CL, CM, CN, CO, CR, CU, CY, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, FR, GA, GB, GD, GE, GH, GM, GN, GQ, GR, GT, GW, HN, HR, HU, ID, IE, IL, IN, IS, IT, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MC, MD, ME, MG, MK, ML, MN, MR, MT, MW, MX, MY, MZ, NA, NE, NG, NI, NL, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SI, SK, SL, SM, SN, ST, SV, SY, SZ, TD, TG, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, UZ, VC, VN, ZA, ZM, ZW)
Inventors:
ABOU GAZALA, Neven M.; US
DIEFENBAUGH, Paul S.; US
JEGANATHAN, Nithyananda S.; US
GORBATOV, Eugene; US
Agent:
KACVINSKY, John; c/o CPA Global PO Box 52050 Minneapolis, Minnesota 55402, US
Priority Data:
Title (EN) TECHNIQUES TO COMPOSE MEMORY RESOURCES ACROSS DEVICES
(FR) TECHNIQUES DE COMPOSITION DE RESSOURCES DE MÉMOIRE ENTRE DES DISPOSITIFS
Abstract:
(EN) Examples are disclosed for composing memory resources across devices. In some examples, memory resources associated with executing one or more applications by circuitry at two separate devices may be composed across the two devices. The circuitry may be capable of executing the one or more applications using a two-level memory (2LM) architecture including a near memory and a far memory. In some examples, the near memory may include near memories separately located at the two devices and a far memory located at one of the two devices. The far memory may be used to migrate one or more copies of memory content between the separately located near memories in a manner transparent to an operating system for the first device or the second device. Other examples are described and claimed.
(FR) Selon des exemples ci-décrits, l'invention se rapporte à la composition de ressources de mémoire entre des dispositifs. Dans certains exemples, des ressources de mémoire associées à l'exécution d'une ou plusieurs applications par un ensemble de circuits sur deux dispositifs distincts peuvent être composées entre ces deux dispositifs. Ledit ensemble de circuits peut être en mesure d'exécuter la ou les applications au moyen d'une architecture de mémoire à deux niveaux (2LM) comprenant une mémoire proche et une mémoire éloignée. Dans certains exemples, la mémoire proche peut comprendre des mémoires proches séparées installées dans les deux dispositifs, et une mémoire éloignée placée dans l'un des deux dispositifs. La mémoire éloignée peut servir à transférer une ou plusieurs copies du contenu de mémoire entre les mémoires proches séparées, et ce d'une manière transparente pour le système d'exploitation (OS) du premier ou du second dispositif. L'invention comporte aussi d'autres exemples.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)