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1. (WO2015045213) THIN FILM TRANSISTOR SUBSTRATE AND METHOD FOR MANUFACTURING SAME
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2015/045213 International Application No.: PCT/JP2014/002789
Publication Date: 02.04.2015 International Filing Date: 27.05.2014
IPC:
H01L 21/336 (2006.01) ,G09F 9/30 (2006.01) ,H01L 29/786 (2006.01) ,H01L 51/50 (2006.01) ,H05B 33/02 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
F
DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
9
Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
30
in which the desired character or characters are formed by combining individual elements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
51
Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
50
specially adapted for light emission, e.g. organic light emitting diodes (OLED) or polymer light emitting devices (PLED)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
B
ELECTRIC HEATING; ELECTRIC LIGHTING NOT OTHERWISE PROVIDED FOR
33
Electroluminescent light sources
02
Details
Applicants:
株式会社JOLED JOLED INC. [JP/JP]; 東京都千代田区神田錦町三丁目23番地 23, Kandanishiki-cho 3-chome, Chiyoda-ku, Tokyo 1010054, JP
Inventors:
岸田 悠治 KISHIDA, Yuji; null
川島 孝啓 KAWASHIMA, Takahiro; null
中崎 能彰 NAKAZAKI, Yoshiaki; null
Agent:
吉川 修一 YOSHIKAWA, Shuichi; 大阪府大阪市淀川区西中島5丁目3番10号タナカ・イトーピア新大阪ビル6階新居国際特許事務所内 c/o NII Patent Firm, 6F, Tanaka Ito Pia Shin-Osaka Bldg.,3-10, Nishi Nakajima 5-chome, Yodogawa-ku, Osaka-city, Osaka 5320011, JP
Priority Data:
2013-20568430.09.2013JP
Title (EN) THIN FILM TRANSISTOR SUBSTRATE AND METHOD FOR MANUFACTURING SAME
(FR) SUBSTRAT DE TRANSISTOR EN COUCHES MINCES ET PROCÉDÉ POUR FABRIQUER CE DERNIER
(JA) 薄膜トランジスタ基板及びその製造方法
Abstract:
(EN) A thin film transistor substrate (100) is provided with: a gate electrode (120), and a first electrode (121) of a capacitor (102), which are formed above a substrate (110) such that the gate electrode and the first electrode are disposed by being aligned with each other in the planar direction of the substrate (110); a gate insulating film (130) that is formed on the gate electrode (120); a semiconductor layer (140) that is formed on the gate insulating film (130); an insulating layer (150) that is formed on the semiconductor layer (140) and above the first electrode (121) such that a part of the semiconductor layer (140) is exposed; a source electrode (160s) and a drain electrode (160d), which are formed above the insulating layer (150) such that the source electrode and the drain electrode are connected to the semiconductor layer (140) at an exposed semiconductor layer (140) portion; and a second electrode (161) of the capacitor (102), said second electrode facing the first electrode (121), and being formed above the insulating layer (150). The film thickness of the insulating layer (150) above the gate electrode (120) is more than that of the insulating layer (150) above the first electrode (121).
(FR) L'invention porte sur un substrat de transistor en couches minces (100) qui comporte : une électrode de grille (120), et une première électrode (121) d'un condensateur (102), qui sont formées au-dessus d'un substrat (110) de telle sorte que l'électrode de grille et la première électrode sont disposées en étant alignées l'une par rapport à l'autre dans la direction planaire du substrat (110); un film d'isolation de grille (130) qui est formé sur l'électrode de grille (120); une couche de semi-conducteur (140) qui est formée sur le film d'isolation de grille (130); une couche d'isolation (150) qui est formée sur la couche de semi-conducteur (140) et au-dessus de la première électrode (121) de telle sorte qu'une partie de la couche de semi-conducteur (140) est présentée; une électrode de source (160s) et une électrode de drain (160d), qui sont formées au-dessus de la couche d'isolation (150) de telle sorte que l'électrode de source et l'électrode de drain sont connectées à la couche de semi-conducteur (140) au niveau d'une partie de couche de semi-conducteur présentée (140); et une seconde électrode (161) du condensateur (102), ladite seconde électrode étant tournée vers la première électrode (121), et étant formée au-dessus de la couche d'isolation (150). L'épaisseur de film de la couche d'isolation (150) au-dessus de l'électrode de grille (120) est supérieure à celle de la couche d'isolation (150) au-dessus de la première électrode (121).
(JA)  薄膜トランジスタ基板(100)は、基板(110)の平面方向に並んで配置されるように、基板(110)の上方に形成されたゲート電極(120)及び容量(102)の第1電極(121)と、ゲート電極(120)上に形成されたゲート絶縁膜(130)と、ゲート絶縁膜(130)上に形成された半導体層(140)と、半導体層(140)の一部が露出するように半導体層(140)上及び第1電極(121)の上方に形成された絶縁層(150)と、半導体層(140)の露出した部分で半導体層(140)と接続されるように絶縁層(150)の上方に形成されたソース電極(160s)及びドレイン電極(160d)と、第1電極(121)に対向し、かつ、絶縁層(150)の上方に形成された容量(102)の第2電極(161)とを備え、ゲート電極(120)上方の絶縁層(150)の膜厚は、第1電極(121)の上方の絶縁層(150)の膜厚より大きい。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)