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Pub. No.: WO/2015/041369 International Application No.: PCT/JP2014/075760
Publication Date: 26.03.2015 International Filing Date: 19.09.2014
IPC:
G11C 16/06 (2006.01) ,G06F 12/00 (2006.01) ,G06F 12/02 (2006.01) ,G11C 15/04 (2006.01) ,G11C 16/02 (2006.01) ,G11C 16/04 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
06
Auxiliary circuits, e.g. for writing into memory
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
02
Addressing or allocation; Relocation
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
15
Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
04
using semiconductor elements
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
04
using variable threshold transistors, e.g. FAMOS
Applicants: KABUSHIKI KAISHA TOSHIBA[JP/JP]; 1-1, Shibaura 1-chome, Minato-ku, Tokyo 1058001, JP
Inventors: MARUKAME, Takao; JP
MATSUZAWA, Kazuya; JP
NISHI, Yoshifumi; JP
CHEN, Jiezhi; JP
HIGASHI, Yusuke; JP
MITANI, Yuuichiro; JP
Agent: SAKAI INTERNATIONAL PATENT OFFICE; JP
Priority Data:
2013-19578920.09.2013JP
Title (EN) MEMORY SYSTEM
(FR) SYSTÈME DE MÉMOIRE
Abstract:
(EN) According to an embodiment, a memory system includes first wiring lines; second wiring lines; third wiring lines; fourth wiring lines; and first and second storages. The first storage includes first memory cells arranged at intersections of the first wiring lines and the second wiring lines. Each of the third wiring lines is connected to any one of the first wiring lines. Each of the fourth wiring lines is pre-associated with a logical address specified by a host apparatus. The second storage includes second memory cells arranged at intersections of the third wiring lines and the fourth wiring lines. A resistance state of each of the second memory cells is set to a first resistance state or a second resistance state where a resistance value is lower than that in the first resistance state, according to a correspondence relationship between the logical address and the first wiring line.
(FR) L'invention concerne, dans un mode de réalisation, un système de mémoire comportant des premières lignes de câblages; des deuxièmes lignes de câblage; des troisièmes lignes de câblage; des quatrièmes lignes de câblage; et des premier et second stockages. Le premier stockage comporte des premières cellules de mémoire agencées à des intersections des premières lignes de câblage et des deuxièmes lignes de câblage. Chacune des troisièmes lignes de câblage est connectée à l'une quelconque des premières lignes de câblage. Chacune des quatrièmes lignes de câblage est pré-associée à une adresse logique spécifiée par un appareil hôte. Le second stockage consiste en des secondes cellules de mémoire agencées à des intersections des troisièmes lignes de câblage et des quatrièmes lignes de câblage. Un état de résistance de chacune des secondes cellules de mémoire est réglé à un premier état de résistance ou à un second état de résistance pour lequel une valeur de résistance est inférieure à la valeur dans le premier état de résistance, selon une relation de correspondance entre l'adresse logique et la première ligne de câblage.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)