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Pub. No.:    WO/2015/041279    International Application No.:    PCT/JP2014/074652
Publication Date: 26.03.2015 International Filing Date: 18.09.2014
H01L 27/00 (2006.01), H01L 27/14 (2006.01), H01L 27/146 (2006.01), H04N 5/369 (2011.01), H04N 5/374 (2011.01)
Applicants: OLYMPUS CORPORATION [JP/JP]; 43-2, Hatagaya 2-chome, Shibuya-ku, Tokyo 1510072 (JP)
Inventors: FUKUOKA Naoto; (JP)
Agent: TANAI Sumio; (JP)
Priority Data:
2013-192904 18.09.2013 JP
(JA) 半導体装置
Abstract: front page image
(EN) This semiconductor device is provided with: a first substrate having a first circuit formed thereupon; a second substrate having a second circuit formed thereupon, and spaced apart from the first substrate; connection parts that are positioned between the first substrate and the second substrate, and electrically connect the first circuit and the second circuit; and a shielding layer that is sandwiched, together with the connection parts, between the first substrate and the second substrate, is positioned so as to surround the connection parts, and is connected to a potential, the value of which is constant in the first substrate and/or the second substrate.
(FR) Selon l'invention, un dispositif semi-conducteur comprend un premier substrat ayant un premier circuit formé sur celui-ci; un second substrat comportant un second circuit formé sur celui-ci, et espacé du premier substrat; des parties de connexion positionnées entre le premier substrat et le second substrat, et connectant électriquement le premier circuit et le second circuit; et une couche de blindage prise en sandwich, conjointement avec les parties de connexion, entre le premier substrat et le second substrat, qui est positionnée de façon à entourer les parties de connexion, et est connectée à un potentiel dont la valeur est constante dans le premier substrat et/ou le second substrat.
(JA) 半導体装置は、第1の回路が形成された第1の基板と、第2の回路が形成され、前記第1の基板と離間して配置された第2の基板と、前記第1の基板と前記第2の基板との間に配置され、前記第1の回路と前記第2の回路とを電気的に接続する接続部と、前記第1の基板と前記第2の基板との間に前記接続部とともに挟まれ、前記接続部を囲むように配置され、前記第1の基板と前記第2の基板との少なくとも一方の基板内の値が一定である電位に接続された遮へい層と、を備える。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)