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1. (WO2015034078) ELECTRONIC-COMPONENT-EQUIPPED SUBSTRATE AND METHOD FOR PRODUCING SAME
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2015/034078 International Application No.: PCT/JP2014/073599
Publication Date: 12.03.2015 International Filing Date: 02.09.2014
IPC:
H01L 21/52 (2006.01) ,H01L 23/12 (2006.01) ,H01L 23/13 (2006.01) ,H05K 3/32 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
52
Mounting semiconductor bodies in containers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
13
characterised by the shape
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
30
Assembling printed circuits with electric components, e.g. with resistor
32
electrically connecting electric components or wires to printed circuits
Applicants: DOWA METALTECH CO., LTD.[JP/JP]; 14-1, Sotokanda 4-chome, Chiyoda-ku, Tokyo 1018617, JP
Inventors: SUNACHI, Naoya; JP
OSANAI, Hideyo; JP
KURITA, Satoru; JP
Agent: OKAWA, Koichi; JP
Priority Data:
2013-18599709.09.2013JP
Title (EN) ELECTRONIC-COMPONENT-EQUIPPED SUBSTRATE AND METHOD FOR PRODUCING SAME
(FR) SUBSTRAT ÉQUIPÉ DE COMPOSANTS ÉLECTRONIQUES ET PROCÉDÉ DE PRODUCTION DE CELUI-CI
(JA) 電子部品搭載基板およびその製造方法
Abstract:
(EN) A method for producing an electronic-component-equipped substrate obtained by mounting an electronic component (14) onto one principal surface of a metal plate (10) comprising copper, or (in the case that a copper-plating film (20) is formed on the front surface thereof) aluminum or an aluminum alloy, wherein: a surface treatment causing surface roughness to be 0.4μm or higher is performed by roughening the one principal surface (or the surface having the copper-plating film (20)) (i.e. the surface to which the electronic component (14) is to be mounted) of the metal plate (10); a silver paste is applied to said principal surface (or the surface having the copper-plating film (20)), and the electronic component (14) is positioned thereon; thereafter, a silver bonding layer (12) is formed by sintering the silver in the silver paste; and the electronic component (14) is bonded to the one principal surface (or the surface having the copper-plating film (20)) of the metal plate (10) by the silver bonding layer (12).
(FR) L'invention concerne un procédé de production d'un substrat équipé de composants électroniques qui est obtenu en montant un composant électronique (14) sur une surface principale d'une plaque métallique (10) comprenant du cuivre, ou (dans le cas où un film de plaquage au cuivre (20) est formé sur sa surface avant) de l'aluminium ou un alliage d'aluminium, dans lequel: un traitement de surface faisant que la rugosité de surface est de 0,4μm ou plus est effectué en dépolissant la surface principale (ou la surface comprenant le film de plaquage au cuivre (20)) (c'est-à-dire la surface sur laquelle le composant électronique (14) doit être monté) de la plaque métallique (10); une pâte d'argent est appliquée sur ladite surface principale (ou la surface comprenant le film de plaquage au cuivre (20)) et le composant électronique (14) est positionné sur celle-ci; une couche de collage à l'argent (12) est ensuite formée par frittage de l'argent dans la pâte d'argent; et le composant électronique (14) est fixé à la surface principale (ou la surface comprenant le film de plaquage au cuivre (20)) de la plaque métallique (10) par la couche de collage à l'argent (12).
(JA) 銅あるいは(表面に銅めっき皮膜20を形成する場合は)アルミニウムまたはアルミニウム合金からなる金属板10の一方の主面に電子部品14が搭載された電子部品搭載基板の製造方法において、金属板10の一方の主面(または銅めっき皮膜20の表面)(電子部品14が接合される面)を粗くしてその表面粗さを0.4μm以上にする表面加工を行い、その主面(または銅めっき皮膜20の表面)に銀ペーストを塗布して電子部品14を配置した後、銀ペースト中の銀を焼結させて銀接合層12を形成し、この銀接合層12によって電子部品14を金属板10の一方の主面(または銅めっき皮膜20の表面)に接合する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)