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1. (WO2015033865) IMAGE CAPTURING DEVICE
PCT Biblio. Data
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Pub. No.:
WO/2015/033865
International Application No.:
PCT/JP2014/072700
Publication Date:
12.03.2015
International Filing Date:
29.08.2014
IPC:
H04N 5/3745
(2011.01),
H03M 1/16
(2006.01)
H
ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
N
PICTORIAL COMMUNICATION, e.g. TELEVISION
5
Details of television systems
30
Transforming light or analogous information into electric information
335
using solid-state image sensors [SSIS]
369
SSIS architecture; Circuitry associated therewith
374
Addressed sensors, e.g. MOS or CMOS sensors
3745
having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
H
ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
M
CODING, DECODING OR CODE CONVERSION, IN GENERAL
1
Analogue/digital conversion; Digital/analogue conversion
12
Analogue/digital converters
14
Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
16
with scale factor modification, i.e. by changing the amplification between the steps
Applicants:
OLYMPUS CORPORATION
[JP/JP]; 43-2, Hatagaya 2-chome, Shibuya-ku, Tokyo 1510072 (JP)
Inventors:
HAGIHARA Yoshio
; (JP)
Agent:
TANAI Sumio
; (JP)
Priority Data:
2013-186523
09.09.2013
JP
Title
(EN)
IMAGE CAPTURING DEVICE
(FR)
DISPOSITIF DE CAPTURE D'IMAGE
(JA)
撮像装置
Abstract:
(EN)
A computing unit performs cyclic A/D conversion in which a first analog signal is amplified by multiplying the first analog signal by an amplification degree (β) (1<β<2), a computation corresponding to a digital value corresponding to the result of a comparison between the magnitude of the first analog signal and a threshold value is executed to output a second analog signal, and a first digital value sequence is outputted. A β estimation unit estimates the value of the amplification degree (β) on the basis of the first digital value sequence corresponding to a β estimation signal. A binary conversion unit acquires a second digital value sequence that is binary numbers on the basis of the first digital value sequence and the estimated value of the amplification degree (β). The computing unit is disposed to correspond to one column or a plurality of columns of an array of a plurality of pixels. A β estimation signal output unit is disposed to correspond to two or more among a plurality of computing units. The β estimation unit is disposed to correspond to two or more among the plurality of computing units. The binary conversion unit is disposed to correspond to two or more among the plurality of computing units.
(FR)
L'invention concerne une unité informatique qui réalise une conversion analogique–numérique (A/N) cyclique dans laquelle un premier signal analogique est amplifié par multiplication du premier signal analogique par un degré d'amplification (β) (1<β<2), un calcul correspondant à une valeur numérique correspondant au résultat d'une comparaison entre l'amplitude du premier signal analogique et une valeur de seuil est exécuté pour délivrer un second signal analogique, et une première séquence de valeurs numériques est délivrée. Une unité d'estimation de β estime la valeur du degré d'amplification (β) sur la base de la première séquence de valeurs numériques correspondant à un signal d'estimation de β. Une unité de conversion binaire acquiert une seconde séquence de valeurs numériques qui correspond à des nombres binaires sur la base de la première séquence de valeurs numériques et de la valeur estimée du degré d'amplification (β). L'unité informatique est disposée de façon à correspondre à une colonne ou à une pluralité de colonnes d'un réseau d'une pluralité de pixels. Une unité d'émission de signal d'estimation de β est disposée de façon à correspondre à au moins deux unités informatiques parmi une pluralité d'unités informatiques. L'unité d'estimation de β est disposée de façon à correspondre à au moins deux unités informatiques parmi la pluralité d'unités informatiques. L'unité de conversion binaire est disposée de façon à correspondre à au moins deux unités informatiques parmi la pluralité d'unités informatiques.
(JA)
演算部は、第1のアナログ信号に増幅度β(1<β<2)を乗じて第1のアナログ信号を増幅するとともに、第1のアナログ信号の大きさと閾値との比較結果に応じたデジタル値に応じた演算を実行して第2のアナログ信号を出力し、第1のデジタル値列を出力する巡回型のAD変換を行う。β推定部は、β推定信号に対応する第1のデジタル値列に基づいて増幅度βの値を推定する。2進化部は、第1のデジタル値列および推定された増幅度βの値に基づいて、2進数である第2のデジタル値列を取得する。演算部は複数の画素の配列の1列または複数列に対応して配置されている。β推定信号出力部は複数の演算部のうちの複数個に対応して配置されている。β推定部は複数の演算部のうちの複数個に対応して配置されている。2進化部は複数の演算部のうちの複数個に対応して配置されている。
Designated States:
AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG).
Publication Language:
Japanese (
JA
)
Filing Language:
Japanese (
JA
)