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Machine translation
1. (WO2015032279) TRENCH SIDEWALL PROTECTION FOR SELECTIVE EPITAXIAL SEMICONDUCTOR MATERIAL FORMATION
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2015/032279    International Application No.:    PCT/CN2014/084794
Publication Date: 12.03.2015 International Filing Date: 20.08.2014
IPC:
H01L 21/336 (2006.01)
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION [US/US]; New Orchard Road, Armonk New York 10504 (US).
IBM (CHINA) CO., LIMITED [CN/CN]; 7F, Bldg 10, ZhangJiang Innovation Park, 399 Keyuan Road, ZhangJiang High-Tech Campus, Pudong New Area Shanghai 201203 (CN) (MG only)
Inventors: CHENG, Kangguo; (US).
DORIS, Bruce B.; (US).
HE, Hong; (US).
KHAKIFIROOZ, Ali; (US)
Agent: ZHONGZI LAW OFFICE; 7F, New Era Building, 26 Pinganli Xidajie, Xicheng District Beijing 100034 (CN)
Priority Data:
14/017,443 04.09.2013 US
Title (EN) TRENCH SIDEWALL PROTECTION FOR SELECTIVE EPITAXIAL SEMICONDUCTOR MATERIAL FORMATION
(FR) PROTECTION DE PAROI DE CREUSET POUR UNE FORMATION DE MATÉRIAU SEMI-CONDUCTEUR ÉPITAXIALE SÉLECTIVE
Abstract: front page image
(EN)A method of forming a semiconductor device includes forming an insulator layer over a substrate; opening a trench in the insulator layer so as to expose one or more semiconductor structures formed on the substrate; forming a protective layer on sidewalls of the trench; subjecting the substrate to a precleaning operation in preparation for epitaxial semiconductor formation, wherein the protective layer prevents expansion of the sidewalls of the trench as a result of the precleaning operation; and forming epitaxial semiconductor material within the trench and over the exposed one or more semiconductor structures.
(FR)L'invention concerne un procédé permettant de former un dispositif semi-conducteur qui consiste à former une couche isolante sur un substrat ; ouvrir un creuset dans la couche isolante afin d'exposer une ou plusieurs structures semi-conductrices formées sur le substrat ; former une couche protectrice sur les parois du creuset ; soumettre le substrat à une opération de pré-nettoyage pour la préparation d'une formation semi-conductrice épitaxiale, la couche protectrice empêchant l'expansion des parois du creuset suite à l'opération de pré-nettoyage ; et former un matériau semi-conducteur épitaxial à l'intérieur du creuset et sur les une ou plusieurs structures semi-conductrices exposées.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)