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1. WO2015024062 - ENHANCED AUTOMATIC IDENTIFICATION SYSTEM

Publication Number WO/2015/024062
Publication Date 26.02.2015
International Application No. PCT/AU2014/000832
International Filing Date 22.08.2014
IPC
H03M 13/00 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING, DECODING OR CODE CONVERSION, IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
G06F 11/10 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
CPC
H03M 13/09
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
09Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
H03M 13/1102
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
11using multiple parity bits
1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
H03M 13/23
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
23using convolutional codes, e.g. unit memory codes
H03M 13/2957
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
29combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
2957Turbo codes and decoding
H03M 13/31
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
31combining coding for error detection or correction and efficient use of the spectrum
H03M 13/6325
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
63Joint error correction and other techniques
6325Error control coding in combination with demodulation
Applicants
  • UNIVERSITY OF SOUTH AUSTRALIA [AU]/[AU]
Inventors
  • GRANT, Alexander, James
  • LECHNER, Gottfried
  • POLLOK, Andre
  • MCKILLIAM, Robert, George
  • LAND, Ingmar, Rudiger
  • HALEY, David, Victor, Lawrie
  • LAVENANT, Marc, Pierre, Denis
Agents
  • MADDERNS
Priority Data
201390321923.08.2013AU
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) ENHANCED AUTOMATIC IDENTIFICATION SYSTEM
(FR) SYSTÈME D'AUTHENTIFICATION AUTOMATIQUE AMÉLIORÉ
Abstract
(EN)
The invention relates to method and apparatus for improving the performance of communication systems using Run Length Limited (RLL) messages such as the existing Automatic Identification System (AlS). A binary data sequence is Forward Error Correction (FEC) coded and then the sequence is compensated, for example by bit-erasure, so that either bit-stuffing is not required, or a bit stuffer will not be activated to ensure that the coded sequence meets the RLL requirement. Various embodiments are described to handle different architectures or input points for the FEC encoder and bit erasure module. The bit erasure module may also add dummy bits to ensure a RLL compliant CRC or to selectively add bits to a reserve buffer to compensate for later bit stuffing in a header. Additional RLL training sequences may also be added to assist in, receiver acquisition.
(FR)
L'invention concerne un procédé et un appareil pour améliorer les performances de systèmes de communication employant des messages à longueur de course limitée (RLL) tels que les systèmes d'identification automatique (AlS) existants. Une séquence de données binaires est codée avec correction d'erreur directe (FEC) et la séquence est ensuite compensée, par exemple par effacement de bit, de sorte que soit le bourrage de bits n'est pas nécessaire, soit un dispositif de bourrage de bits ne sera pas activé afin de garantir que la séquence codée satisfait aux exigences de RLL. Différents modes de réalisation sont décrits pour traiter différentes architectures ou points d'entrée pour le codeur FEC et le module d'effacement des bits. Le module d'effacement des bits peut également ajouter des bits factices pour garantir un CRC conforme RLL ou ajouter de manière sélective des bits à un tampon de réserve afin de compenser le futur bourrage de bits dans un en-tête. Des séquences d'apprentissage RLL supplémentaires peuvent également être ajoutées pour assister dans l'acquisition du récepteur.
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