Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2014210192) DELAY CIRCUIT INDEPENDENT OF SUPPLY VOLTAGE
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2014/210192 International Application No.: PCT/US2014/044146
Publication Date: 31.12.2014 International Filing Date: 25.06.2014
IPC:
H03H 11/26 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
H
IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
11
Networks using active elements
02
Multiple-port networks
26
Time-delay networks
Applicants:
ESS TECHNOLOGY, INC. [US/US]; 48401 Fremont Blvd. Fremont, CA 94538, US
Inventors:
MALLINSON, A., Martin; US
Agent:
GARD, V., Randall; US
Priority Data:
14/314,88225.06.2014US
61/839,30925.06.2013US
Title (EN) DELAY CIRCUIT INDEPENDENT OF SUPPLY VOLTAGE
(FR) CIRCUIT À RETARD INDÉPENDANT DE LA TENSION D'ALIMENTATION
Abstract:
(EN) A delay circuit in which the delay is independent of variations in the power supply which powers the logic gates of the delay circuit is disclosed. By separating the CMOS transistors that form each logic gate by additional CMOS bias transistors which are biased at a controlled voltage, variations in the gate delay of the inverter transistors due to variations in the power supply voltage for the inverter transistors may he minimized, in one embodiment, the constant bias voltage may be provided by a constant current source comprising a series of amplifiers each having a gain significantly less than one connected to a triple cascode.
(FR) Cette invention concerne un circuit à retard dont le retard est indépendant des variations de l'alimentation électrique qui alimente les portes logiques dudit circuit à retard. La séparation des transistors CMOS constituant chaque porte logique par des transistors CMOS à polarisation qui sont polarisés selon une tension contrôlée permet de minimiser les variations du retard de grille des transistors onduleurs sous l'effet des variations de la tension d'alimentation pour les transistors onduleurs et, selon un mode de réalisation, la tension constante de polarisation peut être assurée par une source en courant constant comprenant un ensemble d'amplificateurs dont chacun présente un gain significativement inférieur à un amplificateur connecté à un amplificateur de type triple cascode.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)