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1. (WO2014209404) INTERCONNECT STRUCTURE COMPRISING FINE PITCH BACKSIDE METAL REDISTRIBUTION LINES COMBINED WITH VIAS

Pub. No.:    WO/2014/209404    International Application No.:    PCT/US2013/048792
Publication Date: Thu Jan 01 00:59:59 CET 2015 International Filing Date: Sun Jun 30 01:59:59 CEST 2013
IPC: H01L 21/768
H01L 21/28
H01L 23/48
Applicants: INTEL CORPORATION
Inventors: LEE, Kevin J.
JEONG, James Y.
CHANG, Hsiao-Kang
MUIRHEAD, John
TELANG, Adwait
PURI, Puneesh
KANG, Jiho
PATEL, Nitin M.
Title: INTERCONNECT STRUCTURE COMPRISING FINE PITCH BACKSIDE METAL REDISTRIBUTION LINES COMBINED WITH VIAS
Abstract:
A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a "plate through resist" type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.