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1. (WO2014209398) MAKING A DEFECT FREE FIN BASED DEVICE IN LATERAL EPITAXY OVERGROWTH REGION
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2014/209398 International Application No.: PCT/US2013/048776
Publication Date: 31.12.2014 International Filing Date: 28.06.2013
IPC:
H01L 21/336 (2006.01) ,H01L 29/78 (2006.01) ,H01L 21/20 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
Applicants: INTEL CORPORATION[US/US]; 2200 Mission College Blvd. M/S RNB-4-150 Santa Clara, California 95054, US
Inventors: GOEL, Niti; US
CHU-KUNG, Benjamin; US
DASGUPTA, Sansaptak; US
MUKHERJEE, Niloy; US
METZ, Matthew V.; US
LE, Van H.; US
KAVALIEROS, Jack T.; US
CHAU, Robert S.; US
PILLARISETTY, Ravi; US
Agent: GAZ, Angelo J.; Blakely Sokoloff Taylor & Zafman LLP 1279 Oakmead Parkway Sunnyvale, California 94085, US
Priority Data:
Title (EN) MAKING A DEFECT FREE FIN BASED DEVICE IN LATERAL EPITAXY OVERGROWTH REGION
(FR) FABRICATION D'UN DISPOSITIF À BASE D'AILETTE SANS DÉFAUT DANS UNE RÉGION DE DÉVELOPPEMENT PAR ÉPITAXIE LATÉRALE.
Abstract:
(EN) Electronic device fins may be formed by epitaxially growing a first layer of material on a substrate surface at a bottom of a trench formed between sidewalls of shallow trench isolation (STl) regions. The trench height may be at least 1.5 times its width, and the first layer may fill less than the trench height. Then a second layer of material may be epitaxially grown on the first layer in the trench and over top surfaces of the STl regions. The second layer may have a second width extending over the trench and over portions of top surfaces of the STl regions. The second layer may then be patterned and etched to form a pair of electronic device fins over portions of the top surfaces of the STl regions, proximate to the trench. This process may avoid crystaline defects in the fins due to lattice mismatch in the layer interfaces.
(FR) L'invention concerne des ailettes de dispositifs électroniques pouvant être formées en développant par épitaxie une première couche de matériau sur une surface de substrat situé au fond d'une tranchée formée entre les murs latéraux de régions d'isolation à tranchée peu profonde (STI). La hauteur de la tranchée peut être au moins égale à 1,5 fois sa largeur, et la première couche peut remplir moins que la hauteur de la tranchée. La seconde couche de matériau peut alors être développée par épitaxie sur la première couche dans la tranchée et au-dessus des surfaces supérieurs des régions STI. La seconde couche peut avoir une seconde largeur s'étendant au dessus de la tranchée et au dessus des surfaces supérieures des régions STI. La seconde couche peut être configurée et attaquée pour former une paire d'ailettes de dispositif électronique au dessus des portions des surfaces supérieurs des régions STI, à proximité de la tranchée. Ce procédé peut éviter les défauts cristallins dans les ailettes dus à une mauvaise concordance de matrice dans les interfaces de couche.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)