Search International and National Patent Collections

1. (WO2014209315) MEMORY BUS ERROR SIGNAL

Pub. No.:    WO/2014/209315    International Application No.:    PCT/US2013/048120
Publication Date: Thu Jan 01 00:59:59 CET 2015 International Filing Date: Fri Jun 28 01:59:59 CEST 2013
IPC: G06F 11/08
G06F 13/14
Applicants: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventors: BENEDICT, Melvin K.
Title: MEMORY BUS ERROR SIGNAL
Abstract:
A technique includes receiving, by a device a command, wherein a response to the command is expected from the device within a predetermined response time. The device may selectively generate an error signal to allow time for the device to complete processing the command.