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1. (WO2014209289) NON-PLANAR SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED FIN WITH TOP BLOCKING LAYER
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2014/209289 International Application No.: PCT/US2013/047757
Publication Date: 31.12.2014 International Filing Date: 26.06.2013
IPC:
H01L 29/78 (2006.01) ,H01L 21/336 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
Applicants: INTEL CORPORATION[US/US]; 2200 Mission College Boulevard MS: RNB-4-150 Santa Clara, California 95052, US
Inventors: YEH, Jeng-Ya D.; US
JAN, Chia-Hong; US
HAFEZ, Walid M.; US
PARK, Joodong; US
Agent: BRASK, Justin K.; Blakely, Sokoloff, Taylor & Zafman LLP 1279 Oakmead Parkway Sunnyvale, California 94085-4040, US
Priority Data:
Title (EN) NON-PLANAR SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED FIN WITH TOP BLOCKING LAYER
(FR) DISPOSITIFS À SEMI-CONDUCTEUR NON PLANS AYANT DES AILETTES AUTO-ALIGNÉES AVEC DES COUCHES DE BLOCAGE SUPÉRIEURES
Abstract:
(EN) Non-planar semiconductor devices having self-aligned fins with top blocking layers and methods of fabricating non-planar semiconductor devices having self-aligned fins with top blocking layers are described. For example, a semiconductor structure includes a semiconductor fin disposed above a semiconductor substrate and having a top surface. An isolation layer is disposed on either side of the semiconductor fin, and recessed below the top surface of the semiconductor fin to provide a protruding portion of the semiconductor fin. The protruding portion has sidewalls and the top surface. A gate blocking layer has a first portion disposed on at least a portion of the top surface of the semiconductor fin, and has a second portion disposed on at least a portion of the sidewalls of the semiconductor fin. The first portion of the gate blocking layer is continuous with, but thicker than, the second portion of the gate blocking layer. A gate stack is disposed on the first and second portions of the gate blocking layer.
(FR) La présente invention concerne des dispositifs à semi-conducteur comportant des ailettes auto-alignées avec des couches de blocage supérieures et des procédés de fabrication de dispositifs à semi-conducteur non plans ayant des ailettes auto-alignées avec des couches de blocage supérieures. A titre d'exemple, une structure semi-conductrice comprend une ailette semi-conductrice disposée au-dessus d'un substrat semi-conducteur et ayant une surface supérieure. Une couche d'isolation est disposée de part et d'autre de l'ailette semi-conductrice et est évidée en dessous de la surface supérieure de l'ailette semi-conductrice pour faire en sorte qu'une partie de l'ailette semi-conductrice fasse saillie. La partie faisant saillie présente des parois latérales et la surface supérieure. Une couche de blocage de grille comporte une première partie disposée sur au moins une partie de la surface supérieure de l'ailette semi-conductrice, et comporte une seconde partie disposée sur au moins une partie des parois latérales de l'ailette semi-conductrice. La première partie de la couche de blocage de grille est dans le prolongement de la seconde partie de la couche de blocage de grille mais est plus épaisse que celle-ci. Un empilement de grille est disposé sur les première et seconde parties de la couche de blocage de grille.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)