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1. (WO2014209278) MONOLITHIC THREE-DIMENSIONAL (3D) ICS WITH LOCAL INTER-LEVEL INTERCONNECTS
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2014/209278 International Application No.: PCT/US2013/047542
Publication Date: 31.12.2014 International Filing Date: 25.06.2013
IPC:
H01L 21/768 (2006.01) ,H01L 27/105 (2006.01) ,H01L 21/28 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
Applicants: MORROW, Patrick[US/US]; US (US)
JUN, Kimin[KR/US]; US (US)
WEBB, M. Clair[US/US]; US (US)
NELSON, Donald W.[US/US]; US (US)
INTEL CORPORATION[US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US (AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BE, BF, BG, BH, BJ, BN, BR, BW, BY, BZ, CA, CF, CG, CH, CI, CL, CM, CN, CO, CR, CU, CY, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, FR, GA, GB, GD, GE, GH, GM, GN, GQ, GR, GT, GW, HN, HR, HU, ID, IE, IL, IN, IS, IT, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MC, MD, ME, MG, MK, ML, MN, MR, MT, MW, MX, MY, MZ, NA, NE, NG, NI, NL, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SI, SK, SL, SM, SN, ST, SV, SY, SZ, TD, TG, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, UZ, VC, VN, ZA, ZM, ZW)
Inventors: MORROW, Patrick; US
JUN, Kimin; US
WEBB, M. Clair; US
NELSON, Donald W.; US
Agent: HOWARD, James; Lynch Law Patent Group, P.C. c/o CPA GLOBAL P.O. Box 525050 Minneapolis, Minnesota 55402, US
Priority Data:
Title (EN) MONOLITHIC THREE-DIMENSIONAL (3D) ICS WITH LOCAL INTER-LEVEL INTERCONNECTS
(FR) CIRCUITS INTÉGRÉS TRIDIMENSIONNELS (3D) MONOLITHIQUES AYANT DES INTERCONNEXIONS LOCALES INTER-NIVEAUX
Abstract:
(EN) Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least one transistor level within the 3D IC. In certain embodiments the local inter-level interconnect intersects a gate electrode or a source/drain region of at least one transistor and extends through at least one inter-level dielectric layer disposed between a first and second transistor level in the 3D IC. Local inter-level interconnects may advantageously make a direct vertical connection between transistors in different levels of the 3D IC without being routed laterally around the footprint (i.e., lateral, or planar, area) of either the overlying or underlying transistor level that is interconnected.
(FR) La présente invention se rapporte à des circuits intégrés tridimensionnels (3D) monolithiques utilisant une ou plusieurs interconnexions locales inter-niveaux intimement intégrées à au moins une structure d'au moins un transistor sur au moins un niveau de transistor au sein du circuit intégré 3D. Dans certains modes de réalisation, l'interconnexion locale inter-niveaux présente une intersection avec une électrode de grille ou une région de source/drain d'au moins un transistor et se prolonge à travers au moins une couche diélectrique inter-niveaux disposée entre des premier et second niveaux de transistor dans le circuit intégré 3D. Des interconnexions locales inter-niveaux peuvent avantageusement former une connexion verticale directe entre des transistors se trouvant à différents niveaux du circuit intégré 3D sans qu'elles soient déviées latéralement sur le pourtour de la zone de circuit (c'est-à-dire dans la zone latérale ou planaire) de l'un ou l'autre des niveaux de transistor supérieur ou inférieur qui sont ainsi interconnectés.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)