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1. (WO2014208201) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2014/208201 International Application No.: PCT/JP2014/062129
Publication Date: 31.12.2014 International Filing Date: 02.05.2014
IPC:
H01L 29/861 (2006.01) ,G03F 1/70 (2012.01) ,H01L 21/329 (2006.01) ,H01L 29/06 (2006.01) ,H01L 29/41 (2006.01) ,H01L 29/78 (2006.01) ,H01L 29/868 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
86
controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated, or switched
861
Diodes
G PHYSICS
03
PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
F
PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
1
Originals for photomechanical production of textured or patterned surfaces, e.g. masks, photo-masks or reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
68
Preparation processes not covered by groups G03F1/20-G03F1/5096
70
Adapting basic layout or design of masks to lithographic process requirements, e.g. second iteration correction of mask patterns for imaging
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
328
Multistep processes for the manufacture of devices of the bipolar type, e.g. diodes, transistors, thyristors
329
the devices comprising one or two electrodes, e.g. diodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
86
controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated, or switched
861
Diodes
868
PIN diodes
Applicants: MITSUBISHI ELECTRIC CORPORATION[JP/JP]; 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008310, JP
Inventors: EBIHARA Kohei; JP
MIURA Naruhisa; JP
HAMADA Kenji; JP
OKUNO Koji; JP
Agent: YOSHITAKE Hidetoshi; 10th floor, Sumitomo-seimei OBP Plaza Bldg., 4-70, Shiromi 1-chome, Chuo-ku, Osaka-shi, Osaka 5400001, JP
Priority Data:
2013-13444327.06.2013JP
Title (EN) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
(FR) DISPOSITIF À SEMI-CONDUCTEURS ET SON PROCÉDÉ DE FABRICATION
(JA) 半導体装置およびその製造方法
Abstract:
(EN) The purpose of the present invention is to provide a semiconductor device that is provided with a terminal region where electric field concentration can be effectively relaxed, while suppressing resist collapse during manufacture, and to provide a method for manufacturing the semiconductor device. This semiconductor device is provided with: a semiconductor element (110) formed on a semiconductor substrate formed of a first conductivity-type wide-band-gap semiconductor; and a plurality of second conductivity-type ring-like regions (2), which are formed on the semiconductor substrate (1) by surrounding the semiconductor element (110) in a planar view. At least one of the ring-like regions (2) is provided with one or more separating regions (5) that make the inner side and the outer side of the ring-like region (2) communicate with each other in a planar view.
(FR) Le but de la présente invention est de fournir un dispositif à semi-conducteurs qui comporte une région de borne où une concentration de champ électrique peut être efficacement relâchée, tout en supprimant un affaissement de matière de protection durant la fabrication, et de fournir un procédé pour fabriquer le dispositif à semi-conducteurs. Ce dispositif à semi-conducteurs comporte : un élément de semi-conducteur (110) formé sur un substrat de semi-conducteur formé d’un semi-conducteur à large bande d’énergie interdite d’un premier type de conductivité ; et une pluralité de régions en forme d’anneau d’un second type de conductivité (2), qui sont formées sur le substrat de semi-conducteur (1) en entourant l’élément de semi-conducteur (110) dans une vue en plan. Au moins l’une des régions en forme d’anneau (2) comporte une ou plusieurs régions de séparation (5) qui font communiquer le côté interne et le côté externe de la région en forme d’anneau (2) l’un avec l’autre dans une vue en plan.
(JA)  本発明は、製造時のレジスト倒れを抑制しつつ、電界集中を効果的に緩和することができる終端領域を備えた半導体装置、及びその製造方法の提供を目的とする。本発明の半導体装置は、第1導電型のワイドバンドギャップ半導体からなる半導体基板に形成される半導体素子110と、半導体素子110を平面視で取り囲んで半導体基板1に形成される、第2導電型の複数のリング状領域2とを備え、複数のリング状領域2のうち少なくとも1つは、当該リング状領域2の平面視で内側と外側とを平面視において連通させる1つ以上の離間領域5を備える。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)