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1. (WO2014205904) ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREFOR, AND DISPLAY DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2014/205904 International Application No.: PCT/CN2013/081718
Publication Date: 31.12.2014 International Filing Date: 19.08.2013
IPC:
G02F 1/1333 (2006.01) ,G02F 1/1362 (2006.01) ,H01L 21/77 (2006.01) ,H01L 27/12 (2006.01)
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
1333
Constructional arrangements
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
136
Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
1362
Active matrix addressed cells
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
Applicants: BOE TECHNOLOGY GROUP CO., LTD.[CN/CN]; No.10 Jiuxianqiao Rd., Chaoyang District Beijing 100015, CN
BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.[CN/CN]; No. 118 Jinghaiyilu, BDA Beijing 100176, CN
Inventors: YUAN, Jianfeng; CN
FENG, Yuchun; CN
RIM, Seung Moo; CN
Agent: DRAGON INTELLECTUAL PROPERTY LAW FIRM; Maples International Center 10F, Bldg. 2, No. 32 Xizhimen North Street, Haidian District Beijing 100082, CN
Priority Data:
201310269972.628.06.2013CN
Title (EN) ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREFOR, AND DISPLAY DEVICE
(FR) SUBSTRAT EN RÉSEAU ET SON PROCÉDÉ DE FABRICATION ET DISPOSITIF D'AFFICHAGE
(ZH) 阵列基板及其制造方法和显示装置
Abstract:
(EN) An array substrate, comprising a substrate (11), and a pixel electrode (14), a common electrode (16), a thin-film transistor (13) and a signal line (12) which are arranged on the substrate (11). The signal line (12) comprises a gate line, a data line and a common electrode line. The array substrate further comprises: an insulation layer (15) arranged between the pixel electrode (14) and the common electrode (16). The insulation layer (15) comprises: a first part (151) corresponding to a display area, and a second part (152) corresponding to a non-display area. The non-display area comprises: an area corresponding to the thin-film transistor (13) and the cabling of the signal line (12). The dielectric constant of the first part (151) is greater than a first critical value (ε1), the dielectric constant of the second part (152) is smaller than a second critical value (ε2), and the first critical value (ε1) is greater than the second critical value (ε2). The array substrate can not only reduce the stray capacitance at the cabling of the signal line, but can also solve the problem in the prior art that the drive voltage is higher due to the fact that an organic insulation film is arranged between the pixel electrode and the common electrode. Also provided are a manufacturing method for an array substrate and a display device.
(FR) La présente invention porte sur un substrat en réseau, comprenant un substrat (11) et une électrode (14) de pixel, une électrode (16) commune, un transistor en couches minces (TFT) (13) et une ligne (12) de signal qui sont agencés sur le substrat (10). La ligne (12) de signal comprend une ligne de grille, une ligne de données et une ligne d'électrode commune. Le substrat en réseau comprend en outre : une couche (15) d'isolation agencée entre l'électrode (14) de pixel et l'électrode (16) commune. La couche (15) d'isolation comprend : une première partie (151) correspondant à une zone d'affichage et une seconde partie (152) correspondant à une zone de non affichage. La zone de non affichage comprend : une zone correspondant au TFT (13) et le câblage de la ligne (12) de signal. La constance diélectrique de la première partie (151) est plus grande qu'une première valeur critique (ε1), la constante diélectrique de la seconde partie (152) est plus petite qu'une seconde valeur critique (ε2) et la première valeur critique (ε1) est plus grande que la seconde valeur critique (ε2). Le substrat en réseau peut non seulement réduire la capacité parasite au niveau du câblage de la ligne de signal, mais encore peut résoudre le problème dans l'état antérieur de la technique selon lequel la tension de commande est supérieure en raison du fait qu'un film d'isolation organique est agencé entre l'électrode de pixel et l'électrode commune. La présente invention porte également sur un substrat en réseau et un dispositif d'affichage.
(ZH) 一种阵列基板,包括基板(11),以及设置在基板(11)上的像素电极(14)、公共电极(16)、薄膜晶体管(13)和信号线(12),信号线(12)包括栅线、数据线和公共电极线,阵列基板还包括:设置于像素电极(14)和公共电极(16)之间的绝缘层(15),绝缘层(15)包括:与显示区域对应的第一部分(151)、与非显示区域对应的第二部分(152),非显示区域包括:与薄膜晶体管(13)及信号线(12)走线对应的区域;第一部分(151)的介电常数大于第一临界值(ε1),第二部分(152)的介电常数小于第二临界值(ε2),第一临界值(ε1)大于第二临界值(ε2)。该阵列基板既能降低信号线走线处的寄生电容,又能解决现有技术中因像素电极和公共电极之间的设置有机绝缘膜导致的驱动电压偏高的问题。还提供了一种阵列基板的制造方法和显示装置。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)