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1. (WO2014202886) METHOD FOR TRANSFERRING A LAYER OF CIRCUITS
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2014/202886 International Application No.: PCT/FR2014/051478
Publication Date: 24.12.2014 International Filing Date: 16.06.2014
IPC:
H01L 21/56 (2006.01) ,H01L 21/78 (2006.01) ,H01L 25/00 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
56
Encapsulations, e.g. encapsulating layers, coatings
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
Applicants: SOITEC[FR/FR]; Parc Technologique des Fontaines Chemin des Franques F-38190 Bernin, FR
Inventors: BROEKAART, Marcel; FR
MARINIER, Laurent; FR
Agent: BREESE, Pierre; FR
Priority Data:
135576519.06.2013FR
Title (EN) METHOD FOR TRANSFERRING A LAYER OF CIRCUITS
(FR) PROCÉDÉ DE TRANSFERT D'UNE COUCHE DE CIRCUITS
Abstract:
(EN) The invention relates to a method for transferring a buried layer of circuits (2). Said method is characterised in that it includes the following steps which involve: taking a donor substrate (1, 1') including on the inside an area (7, 7') for halting the etching and covered on one of the surfaces (12) thereof, referred to as "front", with a layer of circuits (2); providing either a peripheral groove (3) that extends away from the side edge (13) of said donor substrate (1, 1') or a peripheral clipping (3') on the entire circumference of said substrate, on the side of the surface thereof covered with the layer of circuits (2), said clipping (3') or said groove (3) being provided deep enough to pass entirely through the layer of circuits (2) and extending into the donor substrate (1, 1'); depositing, on the exposed surface (21) of said layer of circuits (2) and on the clipped surface (13') or on the walls of said groove (3), a layer of a material (4) for selectively halting the etching of said layer of circuits (2), referred to as the "second halting layer", without blocking said groove (3); adhering a receiving substrate (5) to said donor substrate (1, 1') on the side covered by said second halting layer (4); reducing the thickness of the donor substrate (1) by chemical etching of the rear surface thereof (11), until reaching said area (7, 7') for halting the etching, such as to obtain the transfer of said buried layer of circuits (2) to said receiving substrate (5).
(FR) L'invention concerne un procédé de transfert d'une couche de circuits (2) enterrée. Ce procédé est remarquable en ce qu'il comprend les étapes suivantes consistant à : - prendre un substrat donneur (1,1') comprenant intérieurement une zone (7,7') d'arrêt de la gravure et recouvert sur l'une de ses faces (12), dite "avant", d'une couche de circuits (2), - réaliser sur toute la circonférence dudit substrat donneur (1,1'), du côté de sa face recouverte de la couche de circuits (2), soit une tranchée périphérique (3) qui s'étend à distance du bord latéral (13) de ce substrat, soit un détourage périphérique (3'), ce détourage (3') ou cette tranchée (3) étant réalisés sur une profondeur telle qu'ils traversent entièrement la couche de circuits (2) et se prolongent dans le substrat donneur (1,1'), - déposer sur la face exposée (21 ) de ladite couche de circuits (2) et sur la face détourée (13') ou sur les parois de ladite tranchée (3), une couche d'un matériau d'arrêt (4) sélectif vis-à-vis de la gravure de ladite couche de circuits (2), dite "deuxième couche d'arrêt", sans obturer ladite tranchée (3), - coller un substrat receveur (5) sur ledit substrat donneur (1,1') du côté recouvert par ladite deuxième couche d'arrêt (4), - amincir le substrat donneur (1) par gravure chimique de sa face arrière (11), jusqu'à atteindre ladite zone (7,7') d'arrêt de la gravure, de façon à obtenir le transfert de ladite couche de circuits (2) enterrée sur ledit substrat receveur (5).
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: French (FR)
Filing Language: French (FR)