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1. (WO2014199462) SOLAR CELL AND METHOD FOR MANUFACTURING SAME
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2014/199462 International Application No.: PCT/JP2013/066198
Publication Date: 18.12.2014 International Filing Date: 12.06.2013
IPC:
H01L 31/0352 (2006.01) ,H01L 31/074 (2012.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
31
Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength, or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
0248
characterised by their semiconductor bodies
0352
characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
31
Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength, or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
04
adapted as conversion devices
06
characterised by at least one potential-jump barrier or surface barrier
072
the potential barriers being only of the PN heterojunction type
074
comprising a heterojunction with an element of the fourth group of the Periodic System, e.g. ITO/Si, GaAs/Si or CdTe/Si solar cells
Applicants:
株式会社日立製作所 HITACHI, LTD. [JP/JP]; 東京都千代田区丸の内一丁目6番6号 6-6, Marunouchi 1-chome, Chiyoda-ku, Tokyo 1008280, JP
Inventors:
河村 哲史 KAWAMURA, Tetsufumi; JP
峰 利之 MINE, Toshiyuki; JP
渡邉 敬司 WATANABE, Keiji; JP
森下 真年 MORISHITA, Masatoshi; JP
孫 偉 SUN, Wei; JP
服部 孝司 HATTORI, Takashi; JP
長部 太郎 OSABE, Taro; JP
Agent:
筒井 大和 TSUTSUI, Yamato; 東京都新宿区新宿2丁目3番10号 新宿御苑ビル3階 筒井国際特許事務所 Tsutsui & Associates, 3F, Shinjuku Gyoen Bldg., 3-10, Shinjuku 2-chome, Shinjuku-ku, Tokyo 1600022, JP
Priority Data:
Title (EN) SOLAR CELL AND METHOD FOR MANUFACTURING SAME
(FR) CELLULE SOLAIRE ET SON PROCÉDÉ DE FABRICATION
(JA) 太陽電池セルおよびその製造方法
Abstract:
(EN)  A solar cell having a plurality of pillars (NP) formed at a distance from each other in a surface (TS) of an n-type semiconductor substrate (SUB). Each of the pillars (NP) includes a layered part (LB) in which semiconductor layers and material layers having a bandgap differing from that of the semiconductor layers are alternately layered on the surface (TS) of the semiconductor substrate (SUB), and an n-type semiconductor (SCN) and a p-type semiconductor (SCP) formed on a side surface of the layered part (LB). The semiconductor (SCN) is connected to each of a plurality of semiconductor layers and a plurality of material layers exposed on the side surface of the layered part (LB), and the semiconductor (SCP) is connected to each of a plurality of semiconductor layers and a plurality of material layers exposed on the side surface of the layered part (LB).
(FR)  La présente invention concerne une cellule solaire comportant une pluralité de piliers (NP) formés à une certaine distance les uns des autres dans une surface (TS) d'un substrat semi-conducteur de type n (SUB). Chacun des piliers (NP) comprend une partie formée de couches (LB) dans laquelle des couches semi-conductrices et des couches de matériau ayant une bande interdite qui diffère de celle des couches semi-conductrices sont disposées en couches en alternance sur la surface (TS) du substrat semi-conducteur (SUB), et un semi-conducteur de type n (SCN) et un semi-conducteur de type p (SCP) formés sur une surface latérale de la partie formée de couches (LB). Le semi-conducteur (SCN) est connecté à chacune d'une pluralité de couches semi-conductrices et d'une pluralité de couches de matériau exposées sur la surface latérale de la partie formée de couches (LB), et le semi-conducteur (SCP) est connecté à chacune d'une pluralité de couches semi-conductrices et d'une pluralité de couches de matériau exposées sur la surface latérale de la partie formée de couches (LB).
(JA)  太陽電池セルは、n型の半導体基板(SUB)の表面(TS)内で間隔を空けて形成された複数のピラー(NP)を有する。ピラー(NP)は、半導体層と、半導体層と異なるバンドギャップを有する材料層とが、半導体基板(SUB)の表面(TS)上に交互に積層された積層部(LB)と、積層部(LB)の側面に形成された、n型の半導体(SCN)と、p型の半導体(SCP)とを含む。半導体(SCN)は、積層部(LB)の側面に露出した複数の半導体層および複数の材料層のそれぞれと接続されており、半導体(SCP)は、積層部(LB)の側面に露出した複数の半導体層および複数の材料層のそれぞれと接続されている。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)