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1. (WO2014197004) DATA STORAGE ELEMENT AND SIGNAL PROCESSING METHOD

Pub. No.:    WO/2014/197004    International Application No.:    PCT/US2013/069016
Publication Date: Fri Dec 12 00:59:59 CET 2014 International Filing Date: Fri Nov 08 00:59:59 CET 2013
IPC: H03K 3/037
Applicants: SYNOPSYS, INC.
Inventors: DUBEY, Prashant
MITTAL, Shivangi
JHA, Raushan, Kumar
Title: DATA STORAGE ELEMENT AND SIGNAL PROCESSING METHOD
Abstract:
A data storage element comprises a master stage (MS) with a first and a second latch (LI, L2), an error stage (ES) and a slave stage (SLS). The first latch (LI) generates in a clocked fashion based on a clock signal (CLK, CLKT, CLKB) a first logical signal (DOUTl) based on an input signal (DATA) in relation to a first threshold level (TP1). The second latch generates (L2) in a clocked fashion based on the clock signal (CLK, CLKT, CLKB) a second logical signal (DOUT2) based on the input signal (DATA) in relation to a second threshold level (TP2). The second threshold level (TP2) is distinct from the first threshold level (TP1). The error stage provides an error signal (ER) with a first logical state if the first and the second logical signal (DOUTl, DOUT2) have the same logical state, and with a second logical state they have different logical states. The slave stage (SLS) sets an output value (Q) of the data storage element to a common logical state of the first and the second logical signal (DOUTl, DOUT2) when the error signal (ER) has the first logical state, and keeps the output value (Q) unchanged otherwise.