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Machine translation
1. (WO2014193376) SEPARATE MEMORY CONTROLLERS TO ACCESS DATA IN MEMORY
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2014/193376 International Application No.: PCT/US2013/043237
Publication Date: 04.12.2014 International Filing Date: 30.05.2013
IPC:
G06F 13/14 (2006.01) ,G06F 13/38 (2006.01)
Applicants: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP[US/US]; 11445 Compaq Center Drive West Houston, TX 77070, US
Inventors: YOON, Doe Hyun; US
LI, Sheng; US
CHANG, Jichuan; US
CHEN, Ke; US
RANGANATHAN, Parthasarathy; US
JOUPPI, Norman Paul; US
Agent: CHANG, Marcia R.; Hewlett Packard Enterprise 3404 E. Harmony Road Mail Stop 79 Fort Collins, CO 80528, US
Priority Data:
Title (EN) SEPARATE MEMORY CONTROLLERS TO ACCESS DATA IN MEMORY
(FR) CONTROLEURS DE MEMOIRE SEPARES POUR ACCEDER A DES DONNEES EN MEMOIRE
Abstract: front page image
(EN) A first memory controller receives an access command from a second memory controller, where the access command is timing non-deterministic with respect to a timing specification of a memory. The first memory controller sends at least one access command signal corresponding to the access command to the memory, wherein the at least one access command signal complies with the timing specification. The first memory controller determines a latency of access of the memory. The first memory controller sends feedback information relating to the latency to the second memory controller.
(FR) Selon l'invention, un premier contrôleur de mémoire reçoit une commande d'accès en provenance d'un second contrôleur de mémoire, la commande d'accès étant temporellement non déterministe relativement à une spécification de rythme d'une mémoire. Le premier contrôleur de mémoire envoie au moins un signal de commande d'accès correspondant à la commande d'accès à la mémoire, ledit signal de commande d'accès étant conforme à la spécification de minutage. Le premier contrôleur de mémoire détermine une latence d'accès de la mémoire. Le premier contrôleur de mémoire envoie des informations de rétroaction concernant la latence au second contrôleur de mémoire.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)