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1. (WO2014193375) ALLOCATION OF ALIAS REGISTERS IN A PIPELINED SCHEDULE

Pub. No.:    WO/2014/193375    International Application No.:    PCT/US2013/043224
Publication Date: Fri Dec 05 00:59:59 CET 2014 International Filing Date: Fri May 31 01:59:59 CEST 2013
IPC: G06F 9/46
G06F 9/38
G06F 13/16
Applicants: INTEL CORPORATION
Inventors: RONG, Hongbo
WANG, Cheng
PARK, Hyunchul
WU, Youfeng
Title: ALLOCATION OF ALIAS REGISTERS IN A PIPELINED SCHEDULE
Abstract:
In an embodiment, a system includes a processor including one or more cores and a plurality of alias registers to store memory range information associated with a plurality of operations of a loop. The memory range information references one or more memory locations within a memory. The system also includes register assignment means for assigning each of the alias registers to a corresponding operation of the loop, where the assignments are made according to a rotation schedule, and one of the alias registers is assigned to a first operation in a first iteration of the loop and to a second operation in a subsequent iteration of the loop. The system also includes the memory coupled to the processor. Other embodiments are described and claimed.