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1. (WO2014192430) SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2014/192430 International Application No.: PCT/JP2014/060244
Publication Date: 04.12.2014 International Filing Date: 09.04.2014
IPC:
H01L 23/12 (2006.01) ,H01L 21/822 (2006.01) ,H01L 27/04 (2006.01) ,H01L 27/06 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
06
including a plurality of individual components in a non-repetitive configuration
Applicants:
株式会社村田製作所 MURATA MANUFACTURING CO., LTD. [JP/JP]; 京都府長岡京市東神足1丁目10番1号 10-1, Higashikotari 1-chome, Nagaokakyo-shi, Kyoto 6178555, JP
Inventors:
中磯俊幸 NAKAISO, Toshiyuki; JP
加藤登 KATO, Noboru; JP
Agent:
特許業務法人 楓国際特許事務所 KAEDE PATENT ATTORNEYS' OFFICE; 大阪府大阪市中央区農人橋1丁目4番34号 1-4-34, Noninbashi, Chuo-ku, Osaka-shi, Osaka 5400011, JP
Priority Data:
2013-11567431.05.2013JP
2013-22169025.10.2013JP
Title (EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF SEMI-CONDUCTEUR
(JA) 半導体装置
Abstract:
(EN) An ESD protection device (1) comprises the following: an Si substrate (10) on which an ESD protection circuit (10A) has been formed; pads (P1, P2) formed on the Si substrate (10) and for conduction with the ESD protection circuit (10A); a resin layer (22) formed on the Si substrate (10); interlayer connection conductors (232, 242) which conduct electricity to the pads (P1, P2) and which are disposed in contact holes formed in the part of the resin layer (22) where the pads (P1, P2) are positioned; wiring electrodes (231, 241) connected to an outer circumferential part of the interlayer connection conductors (232, 242); external electrodes (25A, 25B) formed on a part of the wiring electrodes (231, 241) at a position different from the interlayer connection conductors (232, 242) in plan view; and a resin layer (26) that is a light transmitting resin in which are formed openings (26A, 26B) for partially exposing the external electrodes (25A, 25B) in plan view. Due to this configuration, provided is a semiconductor device with which breakage of the wiring electrodes or interlayer connection conductors can be confirmed from outside of the device.
(FR) L'invention concerne un dispositif (1) de protection contre les décharges électrostatiques (ESD) comprenant : un substrat Si (10) sur lequel a été formé un circuit de protection ESD (10A); des plots (P1, P2) formés sur le substrat Si (10) pour la conduction avec le circuit de protection ESD (10A); une couche de résine (22) formée sur le substrat Si (10); des conducteurs de connexion intercouche (232, 242) qui conduisent l'électricité aux plots (P1, P2) et qui sont agencés dans des trous de contact formés dans la partie de la couche de résine (22) dans laquelle les plots (P1, P2) sont placés; des électrodes de câblage (231, 241) connectées à une partie circonférentielle extérieure des conducteurs de connexion intercouche (232, 242); des électrodes externes (25A, 25B) formées sur une partie des électrodes de câblage (231, 241) en un emplacement différent de celui des conducteurs de connexion intercouche (232, 242) en vue en plan; et une couche de résine (26) qui est une couche transmettant la lumière dans laquelle sont ménagées des ouvertures (26A, 26B) permettant d'exposer partiellement les électrodes externes (25A, 25B) en vue en plan. Cette configuration permet d'obtenir un dispositif semi-conducteur avec lequel une rupture des électrodes de câblage ou des conducteurs de connexion intercouche peut être confirmée de l'extérieur.
(JA)  ESD保護デバイス(1)は、ESD保護回路(10A)が形成されたSi基板(10)と、Si基板(10)に形成され、ESD保護回路(10A)と導通するパッド(P1,P2)と、Si基板(10)に形成された樹脂層(22)と、パッド(P1,P2)が位置する樹脂層(22)の部分に形成されたコンタクトホールに設けられ、パッド(P1,P2)に導通する層間接続導体(232,242)と、層間接続導体(232,242)の外周部に接続している配線電極(231,241)と、平面視で層間接続導体(232,242)と異なる位置で、配線電極(231,241)上の一部に形成された外部電極(25A,25B)と、平面視で外部電極(25A,25B)の一部を露出させる開口(26A,26B)が形成された透光性樹脂である樹脂層(26)とを備える。これにより、配線電極又は層間接続導体の破断を外観から確認できる半導体装置を提供する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)