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1. (WO2014178652) METHOD FOR MANUFACTURING SUBSTRATE FRAME AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE COMPRISING SAME
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2014/178652    International Application No.:    PCT/KR2014/003863
Publication Date: 06.11.2014 International Filing Date: 30.04.2014
IPC:
H01L 23/495 (2006.01)
Applicants: SEMICON LIGHT CO., LTD. [KR/KR]; 3F, 49, Wongomae-ro 2 beon-gil Giheung-gu Yongin-si Gyeonggi-do 446-901 (KR)
Inventors: PARK, Eun Hyun; (KR).
JEON, Soo Kun; (KR)
Agent: AN, Sang Jeong; First & Forever 7F, Tower A, Advanced Institutes of Convergence Technology 145, Gwanggyo-ro, Yeongtong-gu Suwon-si, Gyeonggi-do 443-270 (KR)
Priority Data:
10-2013-0048117 30.04.2013 KR
Title (EN) METHOD FOR MANUFACTURING SUBSTRATE FRAME AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE COMPRISING SAME
(FR) PROCÉDÉ DE FABRICATION D'UN CADRE DE SUBSTRAT ET PROCÉDÉ DE FABRICATION D'UN DISPOSITIF SEMI-CONDUCTEUR COMPRENANT LEDIT CADRE
(KO) 기판 프레임 제조 방법 및 이를 포함하는 반도체 소자 제조 방법
Abstract: front page image
(EN)The present disclosure relates to a method for manufacturing a substrate frame and a method for manufacturing a semiconductor device comprising same, comprising the steps of: preparing a base and a conductive block comprising two or more conductive pins, each having one end connected to the base and are arranged apart from each other on top of the base; filling an insulation material into a space between the two or more conductive pins and in a space on the periphery of the two or more conductive pins; and forming the substrate frame having an upper surface and a lower surface opposite the upper surface, an insulation portion comprising the insulation material, and two or more conductive portions electrically insulated by the insulation portion, wherein the insulation portion and the two or more conductive portions are connected from the upper surface to the lower surface.
(FR)La présente invention concerne un procédé de fabrication d'un cadre de substrat et un procédé de fabrication d'un dispositif semi-conducteur comprenant ledit cadre, comprenant les étapes suivantes : préparation d'une base et d'un bloc conducteur comprenant au moins deux broches conductrices, chacune ayant une extrémité reliée à la base et lesdites broches étant espacées l'une de l'autre sur la partie supérieure de la base ; remplissage avec un matériau isolant d'un espace situé entre les deux broches conductrices ou plus et d'un espace situé sur la périphérie des deux broches conductrices ou plus ; et formation du cadre de substrat ayant une surface supérieure et une surface inférieure opposée à la surface supérieure, une partie isolante comprenant le matériau isolant, et deux parties conductrices ou plus isolées électriquement par la partie isolante, la partie isolante et les deux parties conductrices ou plus étant reliées de la surface supérieure à la surface inférieure.
(KO)본 개시(MANUFACTURING METHOD OF SUBSTRATE FRAME AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE COMPRISING THE SAME)는, 베이스 및, 각각의 일단부가 베이스에 연결되고 베이스 위에서 서로 떨어져 배열되는, 2 이상의 도전핀을 구비하는 도전 블록을 준비하는 단계; 2 이상의 도전핀 사이의 공간 및 2 이상의 도전핀 둘레의 공간에 절연재료를 채우는 단계; 및 절연재료로 채워진 도전 블록을 절단하여, 상면 및 상면에 대향하는 하면을 가지고, 절연재료로 이루어진 절연부 및 절연부에 의해 전기적으로 절연되는 2 이상의 도전부를 구비하며, 절연부와 2 이상의 도전부가 상면으로부터 하면으로 이어지는 기판 프레임을 형성하는 단계;를 포함하는 것을 특징으로 하는 기판 프레임 제조 방법 및 이를 포함하는 반도체 소자 제조 방법에 관한 것이다.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG).
Publication Language: Korean (KO)
Filing Language: Korean (KO)