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1. WO2014175687 - WIRING FOR SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME

Publication Number WO/2014/175687
Publication Date 30.10.2014
International Application No. PCT/KR2014/003619
International Filing Date 24.04.2014
IPC
H01L 21/28 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
CPC
H01L 21/76805
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
76802by forming openings in dielectrics
76805the opening being a via or contact hole penetrating the underlying conductor
H01L 21/76843
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76838characterised by the formation and the after-treatment of the conductors
76841Barrier, adhesion or liner layers
76843formed in openings in a dielectric
H01L 21/76898
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76898formed through a semiconductor substrate
H01L 23/481
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; ; Selection of materials therefor
481Internal lead connections, e.g. via connections, feedthrough structures
H01L 23/5222
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
5222Capacitive arrangements or effects of, or between wiring layers
H01L 23/5225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
5222Capacitive arrangements or effects of, or between wiring layers
5225Shielding layers formed together with wiring layers
Applicants
  • 전자부품연구원 KOREA ELECTRONICS TECHNOLOGY INSTITUTE [KR]/[KR]
Inventors
  • 김준철 KIM, Jun Chul
  • 김동수 KIM, Dong Su
  • 박세훈 PARK, Se Hoon
  • 육종민 YOOK, Jong Min
Agents
  • 유미특허법인 YOU ME PATENT AND LAW FIRM
Priority Data
10-2013-004635525.04.2013KR
Publication Language Korean (KO)
Filing Language Korean (KO)
Designated States
Title
(EN) WIRING FOR SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME
(FR) CÂBLAGE DE DISPOSITIF À SEMI-CONDUCTEUR ET SON PROCÉDÉ DE FORMATION
(KO) 반도체 소자용 배선 및 그 배선의 형성 방법
Abstract
(EN)
A method of forming wiring for a semiconductor device according to the present invention, comprises: selectively etching a first surface of a silicon substrate to form a predetermined pattern; coating, with a metallic layer, a selected area of the first surface containing a portion where the predetermined pattern is formed; forming an organic material on the first surface to fill an etched portion and cover the coated metallic layer; forming a via hole in the organic material and connecting metallic wiring through the via hole to the coated metallic layer; and grinding a second surface corresponding to the first surface to remove a part of the metallic layer formed in the etched portion.
(FR)
La présente invention concerne un procédé de formation de câblage d'un dispositif à semi-conducteur, qui consiste : en la gravure sélective d'une première surface d'un substrat de silicium pour former un motif prédéterminé ; au revêtement, au moyen d'une couche métallique, d'une zone sélectionnée de la première surface contenant une partie où est formé le motif prédéterminé ; en la formation d'un matériau organique sur la première surface dans le but de remplir une partie gravée et de recouvrir la couche métallique de revêtement ; en la formation d'un trou traversant au niveau du matériau organique et en la connexion d'un câblage métallique à la couche métallique de revêtement par l'intermédiaire du trou traversant ; et au meulage d'une seconde surface correspondant à la première surface pour éliminer une partie de la couche métallique formée dans la partie gravée.
(KO)
본 발명에 따른 반도체 소자용 배선을 형성하는 방법은 실리콘 기판의 제1면을 선택적으로 식각하여 소정의 패턴을 형성하는 단계, 상기 소정의 패턴이 형성된 부분을 포함하는 상기 제1면의 선택된 영역을 금속층으로 코팅하는 단계, 식각된 부분을 채우고 상기 코팅된 금속층을 덮도록, 상기 제1면에 유기물을 형성하는 단계, 상기 유기물에 비아 홀을 형성하고, 상기 비아 홀을 통해서 금속 배선으로 상기 코팅된 금속층과 연결하는 단계, 그리고 식각된 부분에 형성된 금속층의 일부가 제거되도록 상기 제1면과 대응되는 제2면을 갈아내는 단계를 포함한다.
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Latest bibliographic data on file with the International Bureau