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1. WO2014169209 - INTEGRATING MULTI-OUTPUT POWER CONVERTERS HAVING VERTICALLY STACKED SEMICONDUCTOR CHIPS

Publication Number WO/2014/169209
Publication Date 16.10.2014
International Application No. PCT/US2014/033797
International Filing Date 11.04.2014
IPC
H01L 27/02 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H05K 1/02 2006.01
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1Printed circuits
02Details
CPC
H01L 21/50
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
H01L 21/561
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
561Batch processing
H01L 2224/0603
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
06of a plurality of bonding areas
0601Structure
0603Bonding areas having different sizes, e.g. different heights or widths
H01L 2224/29101
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
28Structure, shape, material or disposition of the layer connectors prior to the connecting process
29of an individual layer connector
29001Core members of the layer connector
29099Material
291with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
29101the principal constituent melting at a temperature of less than 400°C
H01L 2224/32245
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32151the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
32221the body and the item being stacked
32245the item being metallic
H01L 2224/37147
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
36Structure, shape, material or disposition of the strap connectors prior to the connecting process
37of an individual strap connector
37001Core members of the connector
37099Material
371with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
37138the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
37147Copper [Cu] as principal constituent
Applicants
  • TEXAS INSTRUMENTS INCORPORATED [US]/[US]
  • TEXAS INSTRUMENTS JAPAN LIMITED [JP]/[JP] (JP)
Inventors
  • DENISON, Marie
  • CARPENTER, Brian, Ashley
  • LOPEZ, Osvaldo, Jorge
  • HERBSOMMER, Juan, Alejandro
  • NOQUIL, Jonathan
Agents
  • FRANZ, Warren, L.
Priority Data
14/181,96617.02.2014US
61/810,86011.04.2013US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) INTEGRATING MULTI-OUTPUT POWER CONVERTERS HAVING VERTICALLY STACKED SEMICONDUCTOR CHIPS
(FR) INTÉGRATION DE CONVERTISSEURS DE PUISSANCE À PLUSIEURS SORTIES SUR LESQUELS DES PUCES SEMI-CONDUCTRICES SONT EMPILÉES VERTICALEMENT
Abstract
(EN)
A packaged multi-output converter (200) comprising a leadframe with a chip pad (201) as ground terminal and a plurality of leads (202) including the electrical input terminal (203); a first FET chip (sync chip, 220) with its source terminal affixed to the leadframe and on its opposite surface a first drain terminal (221) positioned adjacent to a second drain terminal (222), the drain terminals connected respectively by a first (241) and a second (242) metal clip to a first (204) and second (205) output lead; a second FET chip (control chip, 211), positioned vertically over the first drain terminal, with its source terminal attached onto the first clip; a third FET chip (control chip, 212), positioned vertically over the second drain terminal, with its source terminal attached onto the second clip; and the drain terminals (213, 214) of the second and third chips attached onto a third metal clip (260) connected to the input lead (203).
(FR)
L'invention concerne un convertisseur intégré (200) à plusieurs sorties comprenant une grille de connexion avec une plage de connexion (201) en tant que borne à la terre et une pluralité de pattes de sortie (202) incluant la borne électrique d'entrée (203) ; une première puce de FET (chip Sync, 220) avec sa borne source fixée à la grille de connexion et sur sa surface opposée une première borne de drain (221) positionnée adjacente à une seconde borne de drain (222), les bornes de drain étant respectivement connectées par une première (241) et une seconde (242) attache métalliques à une première (204) et une seconde (205) patte de sortie ; une deuxième puce de FET (puce de commande, 211) positionnée verticalement sur la première borne de drain avec sa borne source fixée sur la première attache ; une troisième puce de FET (puce de commande, 212) positionnée verticalement sur la seconde borne de drain avec sa borne source fixée sur la seconde attache ; et les bornes de drain (213, 214) des deuxième et troisième puces fixées sur une troisième attache métallique (260) connectée à la patte d'entrée (203).
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