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1. WO2014130193 - PACKET PROCESSING WITH REDUCED LATENCY

Publication Number WO/2014/130193
Publication Date 28.08.2014
International Application No. PCT/US2014/012643
International Filing Date 23.01.2014
IPC
G06F 13/14 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
G06F 13/24 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
20for access to input/output bus
24using interrupt
CPC
G06F 9/327
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
32Address formation of the next instruction, e.g. by incrementing the instruction counter
322for non-sequential address
327for interrupts
G06F 9/4498
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
44Arrangements for executing specific programs
448Execution paradigms, e.g. implementations of programming paradigms
4498Finite state machines
G06F 9/4812
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
48Program initiating; Program switching, e.g. by interrupt
4806Task transfer initiation or dispatching
4812by interrupt, e.g. masked
G06F 9/526
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
52Program synchronisation; Mutual exclusion, e.g. by means of semaphores
526Mutual exclusion algorithms
H04L 49/90
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
49Packet switching elements
90Queuing arrangements
H04L 49/901
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
49Packet switching elements
90Queuing arrangements
901Storage descriptor, e.g. read or write pointers
Applicants
  • INTEL CORPORATION [US]/[US] (AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BE, BF, BG, BH, BJ, BN, BR, BW, BY, BZ, CA, CF, CG, CH, CI, CL, CM, CN, CO, CR, CU, CY, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, FR, GA, GB, GD, GE, GH, GM, GN, GQ, GR, GT, GW, HN, HR, HU, ID, IE, IL, IN, IR, IS, IT, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MC, MD, ME, MG, MK, ML, MN, MR, MT, MW, MX, MY, MZ, NA, NE, NG, NI, NL, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SI, SK, SL, SM, SN, ST, SV, SY, SZ, TD, TG, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, UZ, VC, VN, ZA, ZM, ZW)
  • TAMIR, Eliezer [US]/[IL] (US)
  • BRANDEBURG, Jesse C. [US]/[US] (US)
  • VASUDEVAN, Anil [IN]/[US] (US)
Inventors
  • TAMIR, Eliezer
  • BRANDEBURG, Jesse C.
  • VASUDEVAN, Anil
Agents
  • PFLEGER, Edmund P.
Priority Data
13/773,25521.02.2013US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) PACKET PROCESSING WITH REDUCED LATENCY
(FR) TRAITEMENT DE PAQUETS À LATENCE RÉDUITE
Abstract
(EN) Generally, this disclosure provides devices, methods and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.
(FR) Généralement, la présente invention concerne des dispositifs, des procédés et des supports lisibles par ordinateur pour le traitement de paquets à latence réduite. Le dispositif peut comprendre une file d'attente de données pour mémoriser des descripteurs de données associés à des paquets de données, les paquets de données devant être transférés entre un réseau et un circuit pilote. Le dispositif peut aussi comprendre un circuit de génération d'interruption pour générer une interruption vers le circuit pilote. L'interruption peut être générée en réponse à une combinaison d'une expiration d'un temporiseur de retard et d'une condition non vide de la file d'attente de données. Le dispositif peut comprendre en outre un registre de retard d'interruption pour permettre au circuit pilote de réinitialiser le temporiseur de retard, la réinitialisation reportant la génération d'interruption.
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