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1. (WO2014129519) PEELING METHOD, SEMICONDUCTOR DEVICE, AND PEELING APPARATUS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2014/129519 International Application No.: PCT/JP2014/053958
Publication Date: 28.08.2014 International Filing Date: 13.02.2014
IPC:
H01L 21/02 (2006.01) ,H01L 21/20 (2006.01) ,H01L 21/336 (2006.01) ,H01L 27/12 (2006.01) ,H01L 29/786 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
Applicants:
SEMICONDUCTOR ENERGY LABORATORY CO., LTD. [JP/JP]; 398, Hase, Atsugi-shi, Kanagawa 2430036, JP
Inventors:
YASUMOTO, Seiji; JP
SATO, Masataka; null
EGUCHI, Shingo; null
SUZUKI, Kunihiko; null
Priority Data:
2013-03140120.02.2013JP
Title (EN) PEELING METHOD, SEMICONDUCTOR DEVICE, AND PEELING APPARATUS
(FR) PROCÉDÉ DE DÉCOLLEMENT, DISPOSITIF SEMI-CONDUCTEUR, ET APPAREIL DE DÉCOLLEMENT
Abstract:
(EN) To improve peelability, yield in a peeling step, and yield in manufacturing a flexible device. A peeling method is employed which includes a first step of forming a peeling layer containing tungsten over a support substrate; a second step of forming, over the peeling layer, a layer to be peeled formed of a stack including a first layer containing silicon oxynitride and a second layer containing silicon nitride in this order and forming an oxide layer containing tungsten oxide between the peeling layer and the layer to be peeled; a third step of forming a compound containing tungsten and nitrogen in the oxide layer by heat treatment; and a fourth step of peeling the peeling layer from the layer to be peeled at the oxide layer.
(FR) La présente invention vise à améliorer la capacité de décollement, le rendement dans une étape de décollement, et le rendement dans la fabrication d'un dispositif souple. A cet effet, l'invention concerne un procédé de décollement qui est utilisé et qui comprend une première étape de formation d'une couche de décollement contenant du tungstène sur un substrat de support ; une deuxième étape de formation, sur la couche de décollement, d'une couche à décoller formée d'un empilement comprenant une première couche contenant de l'oxynitrure de silicium et une seconde couche contenant du nitrure de silicium dans cet ordre et formant une couche d'oxyde contenant de l'oxyde de tungstène entre la couche de décollement et la couche à décoller ; une troisième étape de formation d'un composé contenant du tungstène et de l'azote dans la couche d'oxyde par traitement thermique ; et une quatrième étape de décollement de la couche de décollement à partir de la couche à décoller sur la couche d'oxyde.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)