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1. (WO2014129438) SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2014/129438 International Application No.: PCT/JP2014/053713
Publication Date: 28.08.2014 International Filing Date: 18.02.2014
IPC:
G11C 11/4076 (2006.01) ,G11C 11/407 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21
using electric elements
34
using semiconductor devices
40
using transistors
401
forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063
Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407
for memory cells of the field-effect type
4076
Timing circuits
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21
using electric elements
34
using semiconductor devices
40
using transistors
401
forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063
Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407
for memory cells of the field-effect type
Applicants:
松井 義徳 MATSUI Yoshinori [JP/JP]; JP (US)
ピーエスフォー ルクスコ エスエイアールエル PS4 LUXCO S.A.R.L. [LU/LU]; ルクセンブルク、ヴァル デ ボン マラデス208 208, Val des Bons Malades, Luxembourg 2121, LU
Inventors:
松井 義徳 MATSUI Yoshinori; JP
Agent:
鷲頭 光宏 WASHIZU Mitsuhiro; 東京都中央区銀座一丁目5番1号第三太陽ビル7F Daisan-Taiyo Bldg. 7th Floor, 5-1, Ginza 1-Chome, Chuo-Ku Tokyo 1040061, JP
Priority Data:
2013-03410325.02.2013JP
Title (EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEURS
(JA) 半導体装置
Abstract:
(EN) [Problem] To reduce current consumption caused by generation of an internal clock signal. [Solution] The present invention is provided with: a clock signal buffer circuit (90) which, in response to activation of a chip selection signal (CS_n), starts generation of an internal clock signal PCLKAR; and internal circuits (70, 100, 110, and 120) which operate in synchronization with the internal clock signal PCLKAR. The clock signal buffer circuit (90) suspends generation of the internal clock signal PCLKAR at a second timing if command signals (CA0 to CA9) indicate read commands, and suspends generation of the internal clock signal PCLKAR at a first timing which is earlier than the second timing if the command signals (CA0 to CA9) indicate active commands. According to the present invention, an internal clock signal is generated only for periods necessary in accordance with external command signals, and therefore, it is possible to reduce current consumption.
(FR) La présente invention a pour but de réduire la consommation de courant causée par la génération d'un signal d'horloge interne. A cet effet, la présente invention comprend : un circuit tampon de signal d'horloge (90) qui, en réponse à l'activation d'un signal de sélection de puce (CS_n), démarre la génération d'un signal d'horloge interne PCLKAR; et des circuits internes (70, 100, 110 et 120) qui fonctionnent en synchronisation avec le signal d'horloge interne PCLKAR. Le circuit tampon de signal d'horloge (90) suspend la génération du signal d'horloge interne PCLKAR à un second instant si des signaux de commande (CA0 à CA9) indiquent des commandes de lecture, et suspend la génération du signal d'horloge interne PCLKAR à un premier instant qui est antérieur au second instant si les signaux de commande (CA0 à CA9) indiquent des commandes actives. Selon la présente invention, un signal d'horloge interne est généré seulement pendant des périodes nécessaires en fonction des signaux de commande externes, et en conséquence, il est possible de réduire la consommation de courant.
(JA) 【課題】内部クロック信号の生成によって生じる消費電流を削減する。 【解決手段】チップセレクト信号CS_nの活性化に応答して内部クロック信号PCLKARの生成を開始するクロック信号バッファ回路90と、内部クロック信号PCLKARに同期して動作する内部回路70,100,110,120を備える。クロック信号バッファ回路90は、コマンド信号CA0~CA9がリードコマンドを示している場合には第2のタイミングで内部クロック信号PCLKARの生成を停止し、コマンド信号CA0~CA9がアクティブコマンドを示している場合には第2のタイミングよりも早い第1のタイミングで内部クロック信号PCLKARの生成を停止する。本発明によれば、外部コマンド信号に応じて必要な期間だけ内部クロック信号が生成されることから、消費電流を削減することが可能となる。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)