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1. WO2014125586 - SEMICONDUCTOR DEVICE

Publication Number WO/2014/125586
Publication Date 21.08.2014
International Application No. PCT/JP2013/053439
International Filing Date 13.02.2013
IPC
H01L 29/78 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
78with field effect produced by an insulated gate
H01L 29/12 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02Semiconductor bodies
12characterised by the materials of which they are formed
CPC
H01L 21/046
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
0445the devices having semiconductor bodies comprising crystalline silicon carbide
0455Making n or p doped regions or layers, e.g. using diffusion
046using ion implantation
H01L 29/0634
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
0603characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
0607for preventing surface leakage or controlling electric field concentration
0611for increasing or controlling the breakdown voltage of reverse biased devices
0615by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
063Reduced surface field [RESURF] pn-junction structures
0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
H01L 29/0684
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
0684characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
H01L 29/0878
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
08with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
0843Source or drain regions of field-effect devices
0847of field-effect transistors with insulated gate
0852of DMOS transistors
0873Drain regions
0878Impurity concentration or distribution
H01L 29/0886
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
08with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
0843Source or drain regions of field-effect devices
0847of field-effect transistors with insulated gate
0852of DMOS transistors
0873Drain regions
0886Shape
H01L 29/1095
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
10with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
1095Body region, i.e. base region, of DMOS transistors or IGBTs
Applicants
  • 富士電機株式会社 FUJI ELECTRIC CO., LTD. [JP]/[JP]
Inventors
  • 熊谷 直樹 KUMAGAI, Naoki
Agents
  • 酒井 昭徳 SAKAI, Akinori
Priority Data
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF SEMI-CONDUCTEUR
(JA) 半導体装置
Abstract
(EN)
Upon the front surface of an n+-semiconductor substrate (1) comprising a wide band gap semiconductor, an n--drift region (2) is provided. On the surface layer of the n--drift region (2), p-channel regions (3) are selectively provided. In the interior of the n--drift region (2), high-concentration p+-base regions (4) are provided so as to be in contact with the lower portions of the p-channel regions (3). In the interior of the high-concentration p+-base regions (4), n+-high-concentration regions (11) are selectively provided on the n+-semiconductor substrate (1) side. The n+-high-concentration regions (11) have a striped planar layout extending in the direction in which the high-concentration p+-base regions (4) are aligned. The n+-high-concentration regions (11) are in contact with a JFET region in one end portion of the stripe-longitudinal direction. In addition, the n+-semiconductor substrate (1)-sides of the n+-high-concentration regions (11) are in contact with a portion sandwiched between the high-concentration p+-base regions (4) and the n+-semiconductor substrate (1) among the n--drift regions (2).
(FR)
Selon l'invention, sur la surface avant d'un substrat de semi-conducteur n+ (1) comprenant un semi-conducteur à large bande interdite, une région de dérive n- (2) est agencée. Sur la couche de surface de la région de dérive n- (2), des régions de canal de type p (3) sont agencées de manière sélective. A l'intérieur de la région de dérive n- (2), des régions de base de type p+ à concentration élevée (4) sont agencées de façon à être en contact avec les parties inférieures des régions de canal de type p (3). A l'intérieur des régions de base de type p+ à concentration élevée (4), des régions à concentration élevée de n+ (11) sont agencées de manière sélective sur le côté substrat de semi-conducteur n+ (1). Les régions à concentration élevée de n+ (11) ont une forme plane en bande s'étendant dans la direction dans laquelle les régions de base de type p+ à concentration élevée (4) sont alignées. Les régions à concentration élevée de n+ (11) sont en contact avec une région de JFET dans une partie d'extrémité de la direction longitudinale de bande. De plus, les côtés de substrat de semi-conducteur n+ (1) des régions à concentration élevée de n+ (11) sont en contact avec une partie prise en sandwich entre les régions de base de type p+ à concentration élevée (4) et le substrat de semi-conducteur n+ (1) parmi les régions de dérive n- (2).
(JA)
 ワイドバンドギャップ半導体からなるn+半導体基板(1)のおもて面上には、n-ドリフト領域(2)が設けられている。n-ドリフト領域(2)の表面層にはpチャネル領域(3)が選択的に設けられている。n-ドリフト領域(2)の内部には、pチャネル領域(3)の下部に接するように高濃度p+ベース領域(4)が設けられている。高濃度p+ベース領域(4)の内部には、n+半導体基板(1)側にn+高濃度領域(11)が選択的に設けられている。n+高濃度領域(11)は、高濃度p+ベース領域(4)が並ぶ方向に延びるストライプ状の平面レイアウトを有する。n+高濃度領域(11)は、ストライプ長手方向の一方の端部においてJFET領域に接する。また、n+高濃度領域(11)のn+半導体基板(1)側は、n-ドリフト領域(2)のうち、高濃度p+ベース領域(4)とn+半導体基板(1)とに挟まれた部分に接する。
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