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1. WO2014122601 - IMPROVED NON-VOLATILE MEMORY DEVICE

Publication Number WO/2014/122601
Publication Date 14.08.2014
International Application No. PCT/IB2014/058829
International Filing Date 06.02.2014
IPC
G06F 13/00 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
CPC
G06F 12/0238
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
0223User address space allocation, e.g. contiguous or non contiguous base addressing
023Free address space management
0238Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
G06F 12/126
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
12Replacement control
121using replacement algorithms
126with special data handling, e.g. priority of data or instructions, handling errors or pinning
G06F 13/225
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
20for access to input/output bus
22using successive scanning, e.g. polling
225with priority control
G06F 13/4295
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
42Bus transfer protocol, e.g. handshake; Synchronisation
4282on a serial bus, e.g. I2C bus, SPI bus
4295using an embedded synchronisation
G06F 3/061
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from or digital output to record carriers ; , e.g. RAID, emulated record carriers, networked record carriers
0601Dedicated interfaces to storage systems
0602specifically adapted to achieve a particular effect
061Improving I/O performance
G06F 3/0628
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from or digital output to record carriers ; , e.g. RAID, emulated record carriers, networked record carriers
0601Dedicated interfaces to storage systems
0628making use of a particular technique
Applicants
  • SPANSION LLC.
Inventors
  • KALDERON, Ifat Nitsan
  • WILLIS III, Max Steven
Agents
  • EITAN MEHULAL & SADOT
  • GILLIS, Sally
Priority Data
13/761,21707.02.2013US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) IMPROVED NON-VOLATILE MEMORY DEVICE
(FR) DISPOSITIF DE MÉMOIRE NON VOLATILE AMÉLIORÉ
Abstract
(EN) A non-volatile memory device includes a memory cell array having memory cells distributed among a plurality of sectors and a controller operable to program, read, and erase memory cells in said memory array, the controller further operable to generate and store EPLI values for programming a number of EPLI bits in one of the plurality of sectors with the stored EPLI values. The memory device additionally include a comparator to compare the stored EPLI values with EPLI values programmed in the EPLI bits.
(FR) L'invention concerne un dispositif de mémoire non volatile qui comprend une matrice de cellules de mémoire comprenant des cellules de mémoire distribuées parmi une pluralité de secteurs et un contrôleur utilisable pour programmer, lire et effacer des cellules de mémoire dans ladite matrice de mémoire, le contrôleur étant en outre utilisable pour générer et stocker des valeurs EPLI pour programmer un certain nombre de bits EPLI dans un secteur de la pluralité de secteurs avec les valeurs EPLI stockées. Le dispositif de mémoire comprend de plus un comparateur pour comparer les valeurs EPLI stockées à des valeurs EPLI programmées dans les bits EPLI.
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