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1. WO2014109107 - NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR TESTING SAME

Publication Number WO/2014/109107
Publication Date 17.07.2014
International Application No. PCT/JP2013/078650
International Filing Date 23.10.2013
IPC
G11C 29/42 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation; Testing stores during standby or offline operation
04Detection or location of defective memory elements
08Functional testing, e.g. testing during refresh, power-on self testing or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing
38Response verification devices
42using error correcting codes or parity check
CPC
G06F 11/1048
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
1008in individual solid state devices
1048using arrangements adapted for a specific error detection or correction feature
G06F 11/1068
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
1008in individual solid state devices
1068in sector programmable memories, e.g. flash disk
G06F 11/2215
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
2205using arrangements specific to the hardware being tested
2215to test error correction or detection circuits
G11C 29/36
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing [BIST] ; or interconnection details
36Data generation devices, e.g. data inverters
G11C 29/42
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing [BIST] ; or interconnection details
38Response verification devices
42using error correcting codes [ECC] or parity check
G11C 29/52
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
52Protection of memory contents; Detection of errors in memory contents
Applicants
  • セイコーインスツル株式会社 SEIKO INSTRUMENTS INC. [JP]/[JP]
Inventors
  • 宮城 雅記 MIYAGI, Masanori
  • 山▲崎▼ 太郎 YAMASAKI, Taro
Agents
  • 久原 健太郎 KUHARA, Kentaro
Priority Data
2013-00208309.01.2013JP
Publication Language Japanese (ja)
Filing Language Japanese (JA)
Designated States
Title
(EN) NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR TESTING SAME
(FR) DISPOSITIF DE STOCKAGE À SEMI-CONDUCTEURS NON VOLATIL ET SON PROCÉDÉ DE TEST
(JA) 不揮発性半導体記憶装置及びそのテスト方法
Abstract
(EN) Provided are a nonvolatile semiconductor storage device which can be made smaller with a simple circuit without impairing the function of an error correction unit, and a method for testing the nonvolatile semiconductor storage device. The error correction circuit is configured to perform error detection and correction for only the same number of bits as the number of data bits, and a separate circuit for error detection and correction of check bits is not provided, thereby allowing for smaller circuit size. A multiplexer is provided which, in a testing state, inputs check bits replacing a portion of the data bits read from a storage element array into the error correction circuit so that error detection and correction may be performed for the check bits, thereby allowing an outgoing inspection including the check bits.
(FR) L'invention porte sur un dispositif de stockage à semi-conducteurs non volatil qui peut être rendu plus petit avec un circuit simple sans compromettre la fonction d'une unité de correction d'erreurs, et sur un procédé de test du dispositif de stockage à semi-conducteurs non volatil. Le circuit de correction d'erreurs est configuré pour effectuer une détection et une correction d'erreurs seulement pour le même nombre de bits que le nombre de bits de données, et un circuit séparé de détection et de correction d'erreurs de bits de contrôle n'est pas utilisé, ce qui permet une plus petite taille de circuit. Un multiplexeur est fourni qui, dans un état de test, introduit des bits de contrôle remplaçant une partie des bits de données lus dans une matrice d'éléments de stockage dans le circuit de correction d'erreurs de manière qu'une détection et une correction d'erreurs puissent être effectuées pour les bits de contrôle, ce qui permet une inspection de sortie comprenant les bits de contrôle.
(JA)  誤り訂正部の機能を損なうことなく、簡便な回路で小型化することができる不揮発性半導体記憶装置とそのテスト方法を提供すること。 誤り訂正回路は、データビットと同数のビット数のみの誤り検出と訂正をするように構成し、検査ビットの誤り検出と訂正をする回路を設けないことによって回路を小型化する。そして、テスト状態において、記憶素子アレイから読み出したデータビットの一部と検査ビットを入れ替えて誤り訂正回路に入力するマルチプレクサを設けることで、検査ビットの誤り検出と訂正することによって、検査ビットも含めた出荷検査を可能にした。
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