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1. WO2014107148 - ADAPTIVE DATA PREFETCHING

Publication Number WO/2014/107148
Publication Date 10.07.2014
International Application No. PCT/US2013/020050
International Filing Date 03.01.2013
IPC
G06F 9/06 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
G06F 9/30 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
G06F 12/02 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
CPC
G06F 12/02
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
G06F 12/0862
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0862with prefetch
G06F 2212/6026
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2212Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
60Details of cache memory
6026Prefetching based on access pattern detection, e.g. stride based prefetch
G06F 9/06
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
G06F 9/30
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
G06F 9/3455
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
34Addressing or accessing the instruction operand or the result ; ; Formation of operand address; Addressing modes
345of multiple operands or results
3455using stride
Applicants
  • INTEL CORPORATION [US]/[US] (AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BE, BF, BG, BH, BJ, BN, BR, BW, BY, BZ, CA, CF, CG, CH, CI, CL, CM, CN, CO, CR, CU, CY, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, FR, GA, GB, GD, GE, GH, GM, GN, GQ, GR, GT, GW, HN, HR, HU, ID, IE, IL, IN, IS, IT, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MC, MD, ME, MG, MK, ML, MN, MR, MT, MW, MX, MY, MZ, NA, NE, NG, NI, NL, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SI, SK, SL, SM, SN, ST, SV, SY, SZ, TD, TG, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, UZ, VC, VN, ZA, ZM, ZW)
  • PAVLOU, Demos [CY]/[ES] (US)
  • LOPEZ, Pedro [ES]/[ES] (US)
  • HYUSEINOVA, Mirem, Meyrem [HU]/[ES] (US)
  • LATORRE, Fernando [ES]/[ES] (US)
  • KOSINSKIL, Steffen [DE]/[DE] (US)
  • GOETTSCHE, Ralf [DE]/[DE] (US)
  • MOHANDRU, Varun [DE]/[DE] (US)
Inventors
  • PAVLOU, Demos
  • LOPEZ, Pedro
  • HYUSEINOVA, Mirem, Meyrem
  • LATORRE, Fernando
  • KOSINSKIL, Steffen
  • GOETTSCHE, Ralf
  • MOHANDRU, Varun
Agents
  • TROP, Timothy, N.
Priority Data
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) ADAPTIVE DATA PREFETCHING
(FR) PRÉ-EXTRACTION ADAPTATIVE DE DONNÉES
Abstract
(EN) A system and method for adaptive data prefetching in a processor enables adaptive modification of parameters associated with a prefetch operation. A stride pattern in successive addresses of a memory operation may be detected, including determining a stride length (L). Prefetching of memory operations may be based on a prefetch address determined from a base memory address, the stride length L, and a prefetch distance (D). A number of prefetch misses may be counted at a miss prefetch count (C). Based on the value of the miss prefetch count C, the prefetch distance D may be modified. As a result of adaptive modification of the prefetch distance D, an improved rate of cache hits may be realized.
(FR) L'invention concerne un système et un procédé de pré-extraction adaptative de données dans un processeur permettant une modification adaptative de paramètres associés à une opération de pré-extraction. Un modèle de pas dans des adresses successives d'une opération mémoire peut être détecté, consistant à déterminer une longueur de pas (L). La pré-extraction d'opérations de mémoire peut être basée sur une adresse de pré-extraction déterminée à partir d'une adresse de mémoire de base, la longueur de pas L, et une distance de pré-extraction (D). Un certain nombre d'échecs de pré-extraction peut être compté à un nombre de pré-extractions ratées (C). En fonction de la valeur du nombre de pré-extractions ratées C, la distance de pré-extraction D peut être modifiée. A la suite de la modification adaptative de la distance de pré-extraction D, un taux amélioré d'interceptions cache peut être obtenu.
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