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1. (WO2014100010) INCREASING ION/IOFF RATIO IN FINFETS AND NANO-WIRES
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2014/100010 International Application No.: PCT/US2013/075814
Publication Date: 26.06.2014 International Filing Date: 17.12.2013
IPC:
H01L 21/336 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
Applicants:
SYNOPSYS, INC. [US/US]; 690 E. Middlefield Rd. Mountain View, CA 94043, US
Inventors:
CHOI, Munkang; US
MOROZ, Victor; US
LIN, Xi-wei; US
Agent:
WOLFELD, Warren, S.; Haynes Beffel & Wolfeld LLP P.O. Box 366 Half Moon Bay, CA 94019, US
Priority Data:
13/717,53217.12.2012US
Title (EN) INCREASING ION/IOFF RATIO IN FINFETS AND NANO-WIRES
(FR) AUGMENTATION DE RAPPORT IALLUMÉ/IÉTEINT DANS DES FINFET ET DES NANOFILS
Abstract:
(EN) Roughly described, an integrated circuit transistor structure has a body of semiconductor material, the body having two longitudinally spaced doped source/drain volumes with a channel between, a gate stack disposed outside the body and facing at least one of the surfaces of the body along the channel. The body contains an adjustment volume, longitudinally within the channel volume and spaced behind the first surface by a first distance and spaced longitudinally from both the source/drain volumes. The adjustment volume comprises an adjustment volume material having, at each longitudinal position, an electrical conductivity which differs from that of the adjacent body material at the same longitudinal position, at least while the transistor is in an off-state. In one embodiment the adjustment volume material is a dielectric. In another embodiment the adjustment volume material is an electrical conductor.
(FR) Décrite grossièrement, une structure de transistor de circuit intégré a un corps de matériau de semi-conducteur, le corps ayant deux volumes source/drain dopés espacés de manière longitudinale avec un canal entre ceux-ci, et une pile de grilles disposée à l'extérieur du corps et tournée vers au moins l'une des surfaces du corps le long du canal. Le corps contient un volume de réglage, longitudinalement à l'intérieur du volume de canal et espacé derrière la première surface par une première distance et espacé longitudinalement des deux volumes source/drain. Le volume de réglage comprend un matériau de volume de réglage ayant, au niveau de chaque position longitudinale, une conductivité électrique qui diffère de celle du matériau de corps adjacent au niveau de la même position longitudinale, au moins pendant que le transistor est dans un état éteint. Selon un mode de réalisation, le matériau de volume de réglage est un diélectrique. Selon un autre mode de réalisation, le matériau de volume de réglage est un conducteur électrique.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)