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1. WO2013161892 - SEMICONDUCTOR DEVICE FABRICATION METHOD, THERMALLY INSULATED LOAD JIG, AND THERMALLY INSULATED LOAD JIG MOUNTING METHOD

Publication Number WO/2013/161892
Publication Date 31.10.2013
International Application No. PCT/JP2013/062101
International Filing Date 24.04.2013
Chapter 2 Demand Filed 19.11.2013
IPC
H01L 21/52 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
52Mounting semiconductor bodies in containers
H05K 13/04 2006.01
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
13Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
04Mounting of components
CPC
B23K 37/0426
BPERFORMING OPERATIONS; TRANSPORTING
23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
37Auxiliary devices or processes, not specially adapted to a procedure covered by only one of the preceding main groups
04for holding or positioning work
0426Fixtures for other work
H01L 2224/04026
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
04026Bonding areas specifically adapted for layer connectors
H01L 2224/05082
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
05001Internal layers
05075Plural internal layers
0508being stacked
05082Two-layer arrangements
H01L 2224/05155
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
05001Internal layers
05099Material
051with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
05138the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
05155Nickel [Ni] as principal constituent
H01L 2224/05166
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
05001Internal layers
05099Material
051with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
05163the principal constituent melting at a temperature of greater than 1550°C
05166Titanium [Ti] as principal constituent
H01L 2224/05639
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
05599Material
056with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
05638the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
05639Silver [Ag] as principal constituent
Applicants
  • 日産自動車株式会社 NISSAN MOTOR CO., LTD. [JP]/[JP]
  • サンケン電気株式会社 SANKEN ELECTRIC CO., LTD. [JP]/[JP] (AE, AG, AM, AO, AU, AZ, BB, BF, BH, BJ, BN, BR, BW, BY, BZ, CA, CF, CG, CI, CL, CM, CN, CO, CR, CU, DM, DO, DZ, EC, EG, GA, GD, GE, GH, GM, GN, GQ, GT, GW, HN, ID, IL, IN, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LY, MA, MD, ME, MG, ML, MN, MR, MW, MX, MY, MZ, NA, NE, NG, NI, NZ, OM, PA, PE, PG, PH, QA, RU, RW, SC, SD, SG, SL, SN, ST, SV, SY, SZ, TD, TG, TH, TJ, TM, TN, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW)
  • 富士電機株式会社 FUJI ELECTRIC CO., LTD. [JP]/[JP] (AE, AG, AM, AO, AU, AZ, BB, BF, BH, BJ, BN, BR, BW, BY, BZ, CA, CF, CG, CI, CL, CM, CO, CR, CU, DM, DO, DZ, EC, EG, GA, GD, GE, GH, GM, GN, GQ, GT, GW, HN, ID, IL, IN, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LY, MA, MD, ME, MG, ML, MN, MR, MW, MX, MY, MZ, NA, NE, NG, NI, NZ, OM, PA, PE, PG, PH, QA, RU, RW, SC, SD, SG, SL, SN, ST, SV, SY, SZ, TD, TG, TH, TJ, TM, TN, TT, TZ, UA, UG, UZ, VC, VN, ZA, ZM, ZW)
Inventors
  • 谷本 智 TANIMOTO, Satoshi
  • 図子 祐輔 ZUSHI, Yusuke
  • 村上 善則 MURAKAMI, Yoshinori
  • 松井 康平 MATSUI, Kohei
  • 佐藤 伸二 SATO, Shinji
  • 福島 悠 FUKUSHIMA, Yu
Agents
  • 三好 秀和 MIYOSHI, Hidekazu
Priority Data
2012-10295427.04.2012JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR DEVICE FABRICATION METHOD, THERMALLY INSULATED LOAD JIG, AND THERMALLY INSULATED LOAD JIG MOUNTING METHOD
(FR) PROCÉDÉ DE FABRICATION DE DISPOSITIF À SEMI-CONDUCTEUR, SUPPORT DE SERRAGE À ISOLATION THERMIQUE ET PROCÉDÉ DE MONTAGE DE SUPPORT DE SERRAGE À ISOLATION THERMIQUE
(JA) 半導体装置の製造方法、断熱荷重治具及び断熱荷重治具の設置方法
Abstract
(EN)
This thermally insulated load jig (11) is characterized in that a solder material (14) that has a melting point or a solidus curve temperature within a range of no more than 100°C from the thermal resistance temperature of a semiconductor chip (13) is interposed between a circuit substrate (12) and the semiconductor chip (13), a thermal insulating body (17) is disposed on top of the semiconductor chip (13) being in the condition described above, a metal weight (16) is placed on top of the thermal insulating body (17), and a load is applied to the semiconductor chip (13) while the solder material (14) is being fused and hardened.
(FR)
Cette invention concerne un support de serrage à isolation thermique (11) caractérisé en ce que : un matériau de soudure (14) dont le point de fusion ou une température de courbe de solidus est dans une plage inférieure ou égale à 100 °C par rapport à la température de résistance thermique d'une puce à semi-conducteur (13), est interposé entre un substrat de circuit (12) et ladite puce à semi-conducteur (13); un corps d'isolation thermique (17) est disposé au-dessus de la puce à semi-conducteur (13) qui est dans la position précitée; un poids métallique (16) est disposé au dessus du corps d'isolation thermique (17); et une charge est appliquée à la puce à semi-conducteur (13) pendant que le matériau de soudure (14) est fondu et durci.
(JA)
 本発明の断熱荷重治具11は、半導体チップ13の耐熱温度から100℃以下の範囲内に融点または固相線温度を有するはんだ材料14を、回路基板12と半導体チップ13との間に挟み、この状態の半導体チップ13の上部に熱絶縁体17を設置し、熱絶縁体17の上部に金属錘16を配置して、はんだ材料14を融解させて固化させている間、半導体チップ13に荷重を加えることを特徴とする。
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