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1. (WO2013161892) SEMICONDUCTOR DEVICE FABRICATION METHOD, THERMALLY INSULATED LOAD JIG, AND THERMALLY INSULATED LOAD JIG MOUNTING METHOD
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2013/161892 International Application No.: PCT/JP2013/062101
Publication Date: 31.10.2013 International Filing Date: 24.04.2013
Chapter 2 Demand Filed: 19.11.2013
IPC:
H01L 21/52 (2006.01) ,H05K 13/04 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
52
Mounting semiconductor bodies in containers
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
13
Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
04
Mounting of components
Applicants: NISSAN MOTOR CO., LTD.[JP/JP]; 2, Takara-cho, Kanagawa-ku, Yokohama-shi, Kanagawa 2210023, JP
SANKEN ELECTRIC CO., LTD.[JP/JP]; 6-3, Kitano 3-chome, Niiza-shi, Saitama 3528666, JP (AE, AG, AM, AO, AU, AZ, BB, BF, BH, BJ, BN, BR, BW, BY, BZ, CA, CF, CG, CI, CL, CM, CN, CO, CR, CU, DM, DO, DZ, EC, EG, GA, GD, GE, GH, GM, GN, GQ, GT, GW, HN, ID, IL, IN, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LY, MA, MD, ME, MG, ML, MN, MR, MW, MX, MY, MZ, NA, NE, NG, NI, NZ, OM, PA, PE, PG, PH, QA, RU, RW, SC, SD, SG, SL, SN, ST, SV, SY, SZ, TD, TG, TH, TJ, TM, TN, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW)
FUJI ELECTRIC CO., LTD.[JP/JP]; 1-1, Tanabeshinden, Kawasaki-ku, Kawasaki-shi, Kanagawa 2109530, JP (AE, AG, AM, AO, AU, AZ, BB, BF, BH, BJ, BN, BR, BW, BY, BZ, CA, CF, CG, CI, CL, CM, CO, CR, CU, DM, DO, DZ, EC, EG, GA, GD, GE, GH, GM, GN, GQ, GT, GW, HN, ID, IL, IN, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LY, MA, MD, ME, MG, ML, MN, MR, MW, MX, MY, MZ, NA, NE, NG, NI, NZ, OM, PA, PE, PG, PH, QA, RU, RW, SC, SD, SG, SL, SN, ST, SV, SY, SZ, TD, TG, TH, TJ, TM, TN, TT, TZ, UA, UG, UZ, VC, VN, ZA, ZM, ZW)
Inventors: TANIMOTO, Satoshi; JP
ZUSHI, Yusuke; JP
MURAKAMI, Yoshinori; JP
MATSUI, Kohei; JP
SATO, Shinji; JP
FUKUSHIMA, Yu; JP
Agent: MIYOSHI, Hidekazu; Toranomon Kotohira Tower, 2-8, Toranomon 1-chome, Minato-ku, Tokyo 1050001, JP
Priority Data:
2012-10295427.04.2012JP
Title (EN) SEMICONDUCTOR DEVICE FABRICATION METHOD, THERMALLY INSULATED LOAD JIG, AND THERMALLY INSULATED LOAD JIG MOUNTING METHOD
(FR) PROCÉDÉ DE FABRICATION DE DISPOSITIF À SEMI-CONDUCTEUR, SUPPORT DE SERRAGE À ISOLATION THERMIQUE ET PROCÉDÉ DE MONTAGE DE SUPPORT DE SERRAGE À ISOLATION THERMIQUE
(JA) 半導体装置の製造方法、断熱荷重治具及び断熱荷重治具の設置方法
Abstract:
(EN) This thermally insulated load jig (11) is characterized in that a solder material (14) that has a melting point or a solidus curve temperature within a range of no more than 100°C from the thermal resistance temperature of a semiconductor chip (13) is interposed between a circuit substrate (12) and the semiconductor chip (13), a thermal insulating body (17) is disposed on top of the semiconductor chip (13) being in the condition described above, a metal weight (16) is placed on top of the thermal insulating body (17), and a load is applied to the semiconductor chip (13) while the solder material (14) is being fused and hardened.
(FR) Cette invention concerne un support de serrage à isolation thermique (11) caractérisé en ce que : un matériau de soudure (14) dont le point de fusion ou une température de courbe de solidus est dans une plage inférieure ou égale à 100 °C par rapport à la température de résistance thermique d'une puce à semi-conducteur (13), est interposé entre un substrat de circuit (12) et ladite puce à semi-conducteur (13); un corps d'isolation thermique (17) est disposé au-dessus de la puce à semi-conducteur (13) qui est dans la position précitée; un poids métallique (16) est disposé au dessus du corps d'isolation thermique (17); et une charge est appliquée à la puce à semi-conducteur (13) pendant que le matériau de soudure (14) est fondu et durci.
(JA)  本発明の断熱荷重治具11は、半導体チップ13の耐熱温度から100℃以下の範囲内に融点または固相線温度を有するはんだ材料14を、回路基板12と半導体チップ13との間に挟み、この状態の半導体チップ13の上部に熱絶縁体17を設置し、熱絶縁体17の上部に金属錘16を配置して、はんだ材料14を融解させて固化させている間、半導体チップ13に荷重を加えることを特徴とする。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)