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1. (WO2013161661) MATRIX SUBSTRATE AND DISPLAY DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2013/161661 International Application No.: PCT/JP2013/061474
Publication Date: 31.10.2013 International Filing Date: 18.04.2013
IPC:
G09F 9/30 (2006.01) ,G02F 1/1345 (2006.01)
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
F
DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
9
Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
30
in which the desired character or characters are formed by combining individual elements
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
1333
Constructional arrangements
1345
Conductors connecting electrodes to cell terminals
Applicants:
シャープ株式会社 SHARP KABUSHIKI KAISHA [JP/JP]; 大阪府大阪市阿倍野区長池町22番22号 22-22, Nagaike-cho, Abeno-ku, Osaka-shi, Osaka 5458522, JP
Inventors:
宮本政和 MIYAMOTO Masakazu; null
藤原敏昭 FUJIHARA Toshiaki; null
吉川和広 YOSHIKAWA Kazuhiro; null
浅井芳啓 ASAI Yoshihiro; null
Agent:
特許業務法人池内・佐藤アンドパートナーズ IKEUCHI SATO & PARTNER PATENT ATTORNEYS; 大阪府大阪市北区天満橋1丁目8番30号OAPタワー26階 26th Floor, OAP TOWER, 8-30, Tenmabashi 1-chome, Kita-ku, Osaka-shi, Osaka 5306026, JP
Priority Data:
2012-09979425.04.2012JP
Title (EN) MATRIX SUBSTRATE AND DISPLAY DEVICE
(FR) SUBSTRAT DE MATRICE ET DISPOSITIF D'AFFICHAGE
(JA) マトリクス基板及び表示装置
Abstract:
(EN) A matrix substrate comprises: a pixel area (A); a first wire (G) connected to unidirectionally aligned pixels in the pixel area (A); a second wire (S) connected to pixels aligned in a different direction; a terminal area (17a) in which a terminal is provided for input of a signal; left side lead wires (kS3, kS4) which are wired from the side of the terminal area (17a) to the opposite side by going around the left side of the pixel area (A); and right side lead wires (kS1, kS2) which are wired to the opposite side by going around the right side of the pixel area (A). The left side lead wires and the right side lead wires are connected to the first wire (G) or the second wire (S) through a collection area (D).
(FR) L'invention concerne un substrat de matrice comprenant : une zone de pixels (A) ; un premier fil (G) relié à des pixels alignés de manière unidirectionnelle dans la zone de pixels (A) ; un second fil (S) relié à des pixels alignés dans une direction différente ; une zone de borne (17a) comportant une borne pour l'entrée d'un signal ; des fils conducteurs gauches (kS3, kS4) connectés entre le côté de la zone de borne (17a) et le côté opposé en passant par le côté gauche de la zone de pixels (A) ; et des fils conducteurs droits (kS1, kS2) qui sont connectés au côté opposé en passant par le côté droit de la zone de pixels (A). Les fils conducteurs gauches et les fils conducteurs droits sont reliés au premier fil (G) ou au second fil (S) par le biais d'une zone de jonction (D).
(JA) マトリクス基板は、画素領域(A)と、画素領域(A)において一方向に並んだ画素に接続される第1の配線(G)と、異なる方向に並んだ画素に接続される第2の配線(S)と、信号を入力する端子が設けられる端子領域(17a)と、端子領域(17a)が設けられる側から画素領域(A)の左側を回りこんで反対側へ引き出される左側引き出し線(kS3、kS4)と、右側を回りこんで前記反対側へ引き出される右側引き出し線(kS1、kS2)とを含み、左側引き出し線と右側引き出し線は、集合領域(D)を通って前記第1の配線(G)又は第2の配線(S)へ接続される。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)