Processing

Please wait...

Settings

Settings

Goto Application

1. WO2013161450 - METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR ELEMENT

Publication Number WO/2013/161450
Publication Date 31.10.2013
International Application No. PCT/JP2013/057744
International Filing Date 18.03.2013
IPC
H01L 21/205 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
205using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
C23C 16/42 2006.01
CCHEMISTRY; METALLURGY
23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
16Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes
22characterised by the deposition of inorganic material, other than metallic material
30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
42Silicides
C30B 25/20 2006.01
CCHEMISTRY; METALLURGY
30CRYSTAL GROWTH
BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
25Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour deposition growth
02Epitaxial-layer growth
18characterised by the substrate
20the substrate being of the same materials as the epitaxial layer
H01L 21/027 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
027Making masks on semiconductor bodies for further photolithographic processing, not provided for in group H01L21/18 or H01L21/34165
H01L 21/336 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334Multistep processes for the manufacture of devices of the unipolar type
335Field-effect transistors
336with an insulated gate
H01L 29/12 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02Semiconductor bodies
12characterised by the materials of which they are formed
CPC
C30B 25/186
CCHEMISTRY; METALLURGY
30CRYSTAL GROWTH
BSINGLE-CRYSTAL-GROWTH
25Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
02Epitaxial-layer growth
18characterised by the substrate
186being specially pre-treated by, e.g. chemical or physical means
C30B 25/20
CCHEMISTRY; METALLURGY
30CRYSTAL GROWTH
BSINGLE-CRYSTAL-GROWTH
25Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
02Epitaxial-layer growth
18characterised by the substrate
20the substrate being of the same materials as the epitaxial layer
C30B 29/36
CCHEMISTRY; METALLURGY
30CRYSTAL GROWTH
BSINGLE-CRYSTAL-GROWTH
29Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
10Inorganic compounds or compositions
36Carbides
H01L 21/02378
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02104Forming layers
02365Forming inorganic semiconducting materials on a substrate
02367Substrates
0237Materials
02373Group 14 semiconducting materials
02378Silicon carbide
H01L 21/0243
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02104Forming layers
02365Forming inorganic semiconducting materials on a substrate
02367Substrates
02428Structure
0243Surface structure
H01L 21/02433
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02104Forming layers
02365Forming inorganic semiconducting materials on a substrate
02367Substrates
02433Crystal orientation
Applicants
  • 富士電機株式会社 FUJI ELECTRIC CO., LTD. [JP]/[JP]
  • 独立行政法人産業技術総合研究所 NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY [JP]/[JP]
Inventors
  • 辻 崇 TSUJI, Takashi
  • 福田 憲司 FUKUDA, Kenji
Agents
  • 酒井 昭徳 SAKAI, Akinori
Priority Data
2012-10423627.04.2012JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR ELEMENT
(FR) PROCÉDÉ DE FABRICATION D'UN ÉLÉMENT SEMI-CONDUCTEUR DE CARBURE DE SILICIUM
(JA) 炭化珪素半導体素子の製造方法
Abstract
(EN)
A (000-1)C face having an off-angle θ in the <11-20> direction of an n-type silicon carbide substrate (1) is deemed to be the main face, the surroundings of a portion corresponding to the alignment mark (10) on the main surface layer is selectively removed, and a convex alignment mark (10) is left. The alignment mark (10) has a cross-shaped shape planar shape in which two rectangles, in which the longitudinal direction is tilted from the <11-20> direction by 45°, intersect each other in an orthogonal manner. Next, an epitaxial layer is formed on the upper surface of the alignment mark (10) so as to satisfy Y ≥ X·tanθ where Y represents the film thickness of the p-type epitaxial layer (2), X represents the width of the alignment mark (10) parallel to the main surface of the n-type silicon carbide substrate (1), and θ represents the off-angle of the n-type silicon carbide substrate (1). A stepped part of the atom layer is thereby eliminated from the upper surface of the alignment mark (10), and the entire upper surface of the alignment mark (10) represents the {0001}-face terrace part (10a). It is thereby possible to reduce the size of a silicon carbide semiconductor element.
(FR)
Selon la présente invention, une face (000-1)C qui est dotée d'un angle de décalage θ dans la direction <11-20> d'un substrat de carbure de silicium de type N (1) est considérée comme étant la face principale, la partie environnant une partie correspondant au repère d'alignement (10) sur la couche de surface principale est retirée de façon sélective et un repère d'alignement convexe (10) est laissé. Le repère d'alignement (10) est pourvu d'une forme plane en croix où deux rectangles, dont la direction longitudinale est inclinée par rapport à la direction <11-20> de 45°, se croisent de façon orthogonale. Par la suite, une couche épitaxiale est formée sur la surface supérieure du repère d'alignement (10) de manière à satisfaire la relation Y ≥ X·tanθ où Y représente l'épaisseur de film de la couche épitaxiale de type P (2), X représente la largeur du repère d'alignement (10) qui est parallèle à la surface principale du substrat de carbure de silicium de type N (1) et θ représente l'angle de décalage du substrat de carbure de silicium de type N (1). Une partie à étages de la couche atomique est par conséquent supprimée de la surface supérieure du repère d'alignement (10) et la totalité de la surface supérieure du repère d'alignement (10) représente la partie de terrasse de la face {0001} (10a). Il est par conséquent possible de réduire la taille d'un élément semi-conducteur de carbure de silicium.
(JA)
 n-型炭化珪素基板(1)の<11-20>方向にオフ角θを有する(000-1)C面を主面とし、この主表面層のアライメントマーク(10)となる部分の周囲を選択的に除去し、凸状のアライメントマーク(10)を残す。アライメントマーク(10)は、長手方向が<11-20>方向に対して45度傾いた2つの矩形が直交する十字状の平面形状を有する。次に、p-型エピタキシャル層(2)の膜厚をYとし、アライメントマーク(10)のn-型炭化珪素基板(1)の主表面に平行な幅をXとし、n-型炭化珪素基板(1)のオフ角をθとしたときに、Y≧X・tanθを満たすようにアライメントマーク(10)上面にエピタキシャル層を形成する。これにより、アライメントマーク(10)の上面から原子層のステップ部が消失し、アライメントマーク(10)上面全面が{0001}面テラス部(10a)となる。このようにして、炭化珪素半導体素子の微細化を図ることができる。
Also published as
Latest bibliographic data on file with the International Bureau