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1. WO2013160976 - SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Publication Number WO/2013/160976
Publication Date 31.10.2013
International Application No. PCT/JP2012/007841
International Filing Date 07.12.2012
IPC
H01L 21/3205 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H01L 21/768 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71Manufacture of specific parts of devices defined in group H01L21/7086
768Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/532 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
532characterised by the materials
CPC
H01L 21/764
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
76Making of isolation regions between components
764Air gaps
H01L 21/7682
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
7682the dielectric comprising air gaps
H01L 21/76898
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76898formed through a semiconductor substrate
H01L 2224/0401
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
H01L 2224/0557
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
0556Disposition
0557the external layer being disposed on a via connection of the semiconductor or solid-state body
H01L 2224/13025
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
12Structure, shape, material or disposition of the bump connectors prior to the connecting process
13of an individual bump connector
13001Core members of the bump connector
1302Disposition
13025the bump connector being disposed on a via connection of the semiconductor or solid-state body
Applicants
  • パナソニックIPマネジメント株式会社 PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD. [JP]/[JP]
Inventors
  • 宮島 弘樹 MIYAJIMA, Hiroki
Agents
  • 藤井 兼太郎 FUJII, Kentaro
Priority Data
2012-10109726.04.2012JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
(FR) DISPOSITIF SEMI-CONDUCTEUR ET SON PROCÉDÉ DE FABRICATION
(JA) 半導体装置およびその製造方法
Abstract
(EN)
Stress generated due to a through electrode (18) formed in a semiconductor substrate (11) is relaxed, and fluctuation of transistor characteristics is eliminated. This semiconductor device is provided with: the semiconductor substrate (11); the through electrode (18) formed in the semiconductor substrate (11); an insulating film (15) formed between the semiconductor substrate (11) and the through electrode (18); and the transistor formed on the semiconductor substrate (11) at a predetermined distance from the through electrode (18). A gap (19) is formed in a region in the vicinity of the surface of the semiconductor substrate (11), said region being between the semiconductor substrate (11) and the through electrode (18) and on the insulating film (15).
(FR)
La contrainte générée en raison d'une électrode traversante (18) formée dans un substrat semi-conducteur (11) est atténuée, et la fluctuation des caractéristiques de transistor est éliminée. Le dispositif semi-conducteur selon l'invention comporte : le substrat semi-conducteur (11) ; l'électrode traversante (18) formée dans le substrat semi-conducteur (11) ; une pellicule isolante (15) formée entre le substrat semi-conducteur (11) et l'électrode traversante (18) ; et le transistor formé sur le substrat semi-conducteur (11) à une distance préétablie de l'électrode traversante (18). Un espace (19) est formé dans une zone au voisinage de la surface du substrat semi-conducteur (11), ladite zone étant entre le substrat semi-conducteur (11) et l'électrode traversante (18) et sur la pellicule isolante (15).
(JA)
 半導体基板(11)に形成した貫通電極(18)に起因する応力を緩和し、トランジスタの特性変動を防止する。半導体基板(11)と、半導体基板(11)内に形成された貫通電極(18)と、半導体基板(11)と貫通電極(18)との間に介在するように形成された絶縁膜(15)と、半導体基板(11)上に、貫通電極(18)と所定距離だけ離間して形成されたトランジスタとを備える。半導体基板(11)と貫通電極(18)との間における半導体基板(11)の表面近傍領域であって、かつ、絶縁膜(15)上には、空隙(19)が形成されている。
Also published as
Latest bibliographic data on file with the International Bureau