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1. (WO2013160976) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2013/160976    International Application No.:    PCT/JP2012/007841
Publication Date: 31.10.2013 International Filing Date: 07.12.2012
IPC:
H01L 21/3205 (2006.01), H01L 21/768 (2006.01), H01L 23/522 (2006.01), H01L 23/532 (2006.01)
Applicants: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD. [JP/JP]; 1-61, Shiromi 2-chome, Chuo-ku, Osaka-shi, Osaka 5406207 (JP)
Inventors: MIYAJIMA, Hiroki;
Agent: FUJII, Kentaro; c/o Panasonic Intellectual Property Management Co., Ltd. 1-61, Shiromi 2-chome, Chuo-ku, Osaka-shi, Osaka 5406207 (JP)
Priority Data:
2012-101097 26.04.2012 JP
Title (EN) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
(FR) DISPOSITIF SEMI-CONDUCTEUR ET SON PROCÉDÉ DE FABRICATION
(JA) 半導体装置およびその製造方法
Abstract: front page image
(EN)Stress generated due to a through electrode (18) formed in a semiconductor substrate (11) is relaxed, and fluctuation of transistor characteristics is eliminated. This semiconductor device is provided with: the semiconductor substrate (11); the through electrode (18) formed in the semiconductor substrate (11); an insulating film (15) formed between the semiconductor substrate (11) and the through electrode (18); and the transistor formed on the semiconductor substrate (11) at a predetermined distance from the through electrode (18). A gap (19) is formed in a region in the vicinity of the surface of the semiconductor substrate (11), said region being between the semiconductor substrate (11) and the through electrode (18) and on the insulating film (15).
(FR)La contrainte générée en raison d'une électrode traversante (18) formée dans un substrat semi-conducteur (11) est atténuée, et la fluctuation des caractéristiques de transistor est éliminée. Le dispositif semi-conducteur selon l'invention comporte : le substrat semi-conducteur (11) ; l'électrode traversante (18) formée dans le substrat semi-conducteur (11) ; une pellicule isolante (15) formée entre le substrat semi-conducteur (11) et l'électrode traversante (18) ; et le transistor formé sur le substrat semi-conducteur (11) à une distance préétablie de l'électrode traversante (18). Un espace (19) est formé dans une zone au voisinage de la surface du substrat semi-conducteur (11), ladite zone étant entre le substrat semi-conducteur (11) et l'électrode traversante (18) et sur la pellicule isolante (15).
(JA) 半導体基板(11)に形成した貫通電極(18)に起因する応力を緩和し、トランジスタの特性変動を防止する。半導体基板(11)と、半導体基板(11)内に形成された貫通電極(18)と、半導体基板(11)と貫通電極(18)との間に介在するように形成された絶縁膜(15)と、半導体基板(11)上に、貫通電極(18)と所定距離だけ離間して形成されたトランジスタとを備える。半導体基板(11)と貫通電極(18)との間における半導体基板(11)の表面近傍領域であって、かつ、絶縁膜(15)上には、空隙(19)が形成されている。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)