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1. WO2013158557 - ERASE OPERATION FOR 3D NON VOLATILE MEMORY WITH CONTROLLABLE GATE-INDUCED DRAIN LEAKAGE CURRENT

Publication Number WO/2013/158557
Publication Date 24.10.2013
International Application No. PCT/US2013/036616
International Filing Date 15.04.2013
IPC
G11C 16/06 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
G11C 5/02 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by group G11C11/63
02Disposition of storage elements, e.g. in the form of a matrix array
H01L 27/115 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
G11C 16/04 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
04using variable threshold transistors, e.g. FAMOS
G11C 16/34 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
CPC
G11C 16/0483
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
04using variable threshold transistors, e.g. FAMOS
0483comprising cells having several storage transistors connected in series
G11C 16/06
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
G11C 16/14
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
10Programming or data input circuits
14Circuits for erasing electrically, e.g. erase voltage switching circuits
G11C 16/3445
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
3436Arrangements for verifying correct programming or erasure
344Arrangements for verifying correct erasure or for detecting overerased cells
3445Circuits or methods to verify correct erasure of nonvolatile memory cells
G11C 16/3472
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
3436Arrangements for verifying correct programming or erasure
3468Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
3472Circuits or methods to verify correct erasure of nonvolatile memory cells whilst erasing is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasure
G11C 5/02
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
02Disposition of storage elements, e.g. in the form of a matrix array
Applicants
  • SANDISK TECHNOLOGIES, INC. [US]/[US]
  • COSTA, Xiying [US]/[US] (US)
  • LI, Haibo [CN]/[US] (US)
  • HIGASHITANI, Masaaki [JP]/[US] (US)
  • MUI, Man, L. [US]/[US] (US)
Inventors
  • COSTA, Xiying
  • LI, Haibo
  • HIGASHITANI, Masaaki
  • MUI, Man, L.
Agents
  • MAGEN, Burt
Priority Data
13/450,31318.04.2012US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) ERASE OPERATION FOR 3D NON VOLATILE MEMORY WITH CONTROLLABLE GATE-INDUCED DRAIN LEAKAGE CURRENT
(FR) OPÉRATION D'EFFACEMENT RÉALISÉE AVEC UN COURANT DE FUITE DE DRAIN INDUIT PAR LA GRILLE POUVANT ÊTRE RÉGULÉ ET DESTINÉE À UNE MÉMOIRE NON VOLATILE EN 3D
Abstract
(EN)
An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in erase iterations of the erase operation. Vgidl can be stepped up when a specified portion of the cells have reached the erase verify level. In this case, a majority of the cells may have reached the erase verify level, such that the remaining cells can benefit from a higher gate- induced drain leakage (GIDL) current to reached the erase verify level. Verase can step up before and, optionally, after Vigdl is stepped up, but remain fixed while Vgidl is stepped. Vgidl can be stepped up until a maximum allowed level, Vgidl_max, is reached. Vgidl may be applied to a drain-side and/or source-side of a NAND string via a bit line or source line, respectively.
(FR)
Une opération d'effacement destinée à un dispositif de mémoire à superposition en 3D applique à un ensemble de cellules de mémoire une impulsion d'effacement qui comporte un niveau intermédiaire (Vgidl) et un niveau de crête (Verase) et augmente Vgidl au cours d'itérations d'effacement de l'opération d'effacement. Vgidl peut être augmenté quand une partie spécifiée des cellules a atteint le niveau de vérification d'effacement. Dans ce cas, une majorité des cellules peut avoir atteint le niveau de vérification d'effacement, de sorte que les autres cellules peuvent bénéficier d'un courant de fuite de drain induit par la grille (GIDL) supérieur pour atteindre le niveau de vérification d'effacement. Verase peut augmenter avant et, éventuellement, après l'augmentation de Vgidl, mais Verase reste fixe pendant que Vgidl augmente. Vgidl peut être augmenté jusqu'à ce qu'un niveau maximum admissible, Vgidl_max, soit atteint. Vgidl peut être appliqué à un côté de drain et/ou à un côté de source d'une chaîne NON-ET par l'intermédiaire d'une ligne de binaire ou d'une ligne de source respectivement.
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