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1. (WO2013158556) SOFT ERASE OPERATION FOR 3D NON-VOLATILE MEMORY WITH SELECTIVE INHIBITING OF PASSED BITS

Pub. No.:    WO/2013/158556    International Application No.:    PCT/US2013/036615
Publication Date: Fri Oct 25 01:59:59 CEST 2013 International Filing Date: Tue Apr 16 01:59:59 CEST 2013
IPC: G11C 16/16
G11C 5/02
H01L 27/115
G11C 16/04
G11C 16/34
Applicants: SANDISK TECHNOLOGIES, INC.
COSTA, Xiying
LI, Haibo
HIGASHITANI, Masaaki
MUI, Man, L.
Inventors: COSTA, Xiying
LI, Haibo
HIGASHITANI, Masaaki
MUI, Man, L.
Title: SOFT ERASE OPERATION FOR 3D NON-VOLATILE MEMORY WITH SELECTIVE INHIBITING OF PASSED BITS
Abstract:
An erase operation for a 3D stacked memory device selectively inhibits subsets of memory cells which meet a verify condition as the erase operation progresses. As a result, the faster-erasing memory cells are less likely to be over-erased and degradation is reduced. Each subset of memory cells can be independently erased by controlling a select gate, drain (SGD) transistor line, a bit line or a word line, according to the type of subset. For a SGD line subset or a bit line subset, the SGD line or bit line, respectively, is set at a level which inhibits erase. For a word line subset, the word line voltage is floated to inhibit erase. An inhibit or uninhibit status can be maintained for each subset, and each type of subset can have a different maximum allowable number of fail bits.