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1. (WO2013157693) SELF-HEALING, FAULT-TOLERANT FPGA COMPUTATION UNIT AND STRUCTURE
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2013/157693 International Application No.: PCT/KR2012/004444
Publication Date: 24.10.2013 International Filing Date: 05.06.2012
IPC:
H03K 19/173 (2006.01) ,G06F 11/07 (2006.01)
Applicants: LEE, Jeong A[KR/KR]; KR (UsOnly)
HASAN, Baig[PK/PK]; PK (UsOnly)
INDUSTRY-ACADEMIC COOPERATION FOUNDATION CHOSUN UNIVERSITY[KR/KR]; 309, Pilmun-daero, Dong-gu Gwangju 501-759, KR (AllExceptUS)
Inventors: LEE, Jeong A; KR
HASAN, Baig; PK
Agent: IAM PATENT FIRM; (Hyejeon Bldg, Yeoksam-dong) 502, 224 Bongeunsa-ro, Gangnam-gu Seoul 135-080, KR
Priority Data:
10-2012-004103319.04.2012KR
10-2012-004162620.04.2012KR
10-2012-005914301.06.2012KR
Title (EN) SELF-HEALING, FAULT-TOLERANT FPGA COMPUTATION UNIT AND STRUCTURE
(FR) UNITÉ DE CALCUL ET STRUCTURE FPGA À AUTORÉGÉNÉRATION AVEC TOLÉRANCE DE PANNES
(KO) 자가치유형 오류 허용 에프피지에이 연산 유닛 및 구조
Abstract: front page image
(EN) The present invention relates to a computation unit and a self-healing, fault-tolerant FPGA structure and, more particularly, to a computation unit and an FPGA including the same, which can detect a temporary internal error or permanent internal error by inputting a first function and a second function and comparing a prestored error detection code with a generated error detection code signal. The computation unit and the self-healing, fault-tolerant FPGA structure of the present invention can reconfigure stem cells and lookup tables included in the computation unit and can output a normal output signal even if a temporary error or a permanent error is generated in an computation cell such that the corresponding computation cell and an computation tile can be normally operated.
(FR) La présente invention concerne une unité de calcul ainsi qu'une structure FPGA à autorégénération avec tolérance de pannes et, plus particulièrement, une unité de calcul et un FPGA incluant ladite unité qui peuvent détecter une erreur interne temporaire ou permanente en entrant une première fonction et une seconde fonction et en comparant un code de détection d'erreur pré-enregistré avec un signal de code de détection d'erreur généré. L'unité de calcul et la structure FGPA à autorégénération avec tolérance de pannes de la présente invention peuvent reconfigurer des cellules souches et des tables de recherche incluses dans l'unité de calcul et générer un signal de sortie normale, même si une erreur temporaire ou permanente est générée dans une cellule de calcul, de sorte que la cellule de calcul correspondante et un pavé de calcul peuvent fonctionner normalement.
(KO) 본 발명은 연산 유닛 및 자가치유형 오류 허용 FPGA 구조에 관한 것으로, 제1 함수 및 제2 함수를 입력받아 미리 저장된 에러검출코드와 생성된 에러검출코드 신호를 비교하여 내부의 일시오류 또는 영구오류를 검출하는 연산 유닛 및 이를 포함하는 FPAG를 제공할 수 있다. 본 발명의 연산 유닛 및 자가치유형 오류 허용 FPGA 구조는 스템셀 및 연산 유닛에 포함된 룩업테이블의 재구성이 가능하고, 연산셀에 일시적 오류 또는 영구적 오류가 발생하여도 정상적인 출력신호를 출력하여, 해당 연산셀 및 연산타일이 정상적으로 동작할 수 있다.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Korean (KO)
Filing Language: Korean (KO)