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1. (WO2013157527) DRIVE CIRCUIT, ELECTRO-OPTIC DEVICE, ELECTRONIC DEVICE, AND DRIVE METHOD
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2013/157527 International Application No.: PCT/JP2013/061230
Publication Date: 24.10.2013 International Filing Date: 15.04.2013
IPC:
G09G 3/30 (2006.01) ,G09G 3/20 (2006.01) ,H01L 51/50 (2006.01)
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20
for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
22
using controlled light sources
30
using electroluminescent panels
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20
for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
51
Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
50
specially adapted for light emission, e.g. organic light emitting diodes (OLED) or polymer light emitting devices (PLED)
Applicants:
三星ディスプレイ株式會社 Samsung Display Co., Ltd. [KR/KR]; 京畿道龍仁市器興区三星ニ路95 95, Samsung 2 Ro, Giheung-Gu, Yongin-City, Gyeonggi-Do, KR
Inventors:
神田 栄二 Kanda Eiji; JP
奥野 武志 Okuno Takeshi; JP
古宮 直明 Komiya Naoaki; JP
Agent:
特許業務法人高橋・林アンドパートナーズ TAKAHASHI, HAYASHI AND PARTNER PATENT ATTORNEYS, INC.; 東京都大田区蒲田5-24-2 損保ジャパン蒲田ビル9階 Sonpo Japan Kamata Building 9F, 5-24-2 Kamata, Ota-ku, Tokyo 1440052, JP
Priority Data:
2012-09266616.04.2012JP
Title (EN) DRIVE CIRCUIT, ELECTRO-OPTIC DEVICE, ELECTRONIC DEVICE, AND DRIVE METHOD
(FR) CIRCUIT ET PROCÉDÉ D'ENTRAÎNEMENT, DISPOSITIF ÉLECTRO-OPTIQUE ET DISPOSITIF ÉLECTRONIQUE
(JA) 駆動回路、電気光学装置、電子機器、および駆動方法
Abstract:
(EN) This drive circuit is provided with: pixel circuits; n data lines (where n is an integer of two or more) provided correspondingly for the pixel circuits of each column; gate lines to which scanning signals are supplied; and light emission control lines to which light emission control signals are supplied. The pixel circuits of a plurality of rows are exclusively connected to each n data lines provided correspondingly to the pixel circuits of each column. Each pixel circuit comprises: a write control transistor that controls the writing of a data voltage according to the scanning signal; a drive transistor that controls the amount of current to be supplied to a current light-emitting element; a light emission control transistor that controls whether or not current is supplied to the current light-emitting element according to the light emission control signal; a capacitive element that holds a voltage corresponding to the data voltage; and a reset transistor for setting a gate electrode of the drive transistor to an initial voltage.
(FR) La présente invention concerne un circuit d'entraînement équipé : de circuits de pixels; de n lignes de données (où n est un entier égal à deux ou plus) prévues de façon correspondante pour les circuits de pixels de chaque colonne; de lignes de grille auxquelles des signaux de balayage sont fournis; et de lignes de commande d'émission lumineuse, auxquelles des signaux de commande d'émission lumineuse sont fournis. Les circuits de pixels d'une pluralité de rangées sont connectés exclusivement à chaque n ligne de données, en correspondance avec les circuits de pixels de chaque colonne. Chaque circuit de pixels comprend : un transistor de commande d'écriture, qui commande l'écriture d'une tension de données, en fonction du signal de balayage; un transistor d'entraînement, qui commande la quantité de courant à fournir à un élément électroluminescent de courant; un transistor de commande d'émission de lumière qui commande si oui ou non le courant est fourni à l'élément électroluminescent de courant, en fonction du signal de commande d'émission lumineuse; un élément capacitif, qui maintient une tension correspondant à la tension de données; et un transistor de réinitialisation, destiné à régler une électrode de grille du transistor d'entraînement sur une tension initiale.
(JA)  本発明の駆動回路は、画素回路と、各列の画素回路に対応してn本(nは2以上の整数)ずつ設けられたデータ線と、走査信号が供給されるゲート線と、発光制御信号が供給される発光制御線とを備え、各列の画素回路に対応して設けられたn本のデータ線の各々には、複数の行の画素回路が排他的に接続され、画素回路は、走査信号に応じてデータ電圧の書き込みを制御する書込制御トランジスタと、電流発光素子へ供給される電流量を制御する駆動トランジスタと、発光制御信号に応じて、電流発光素子への電流供給の有無を制御する発光制御トランジスタと、データ電圧に応じた電圧を保持する容量素子と、駆動トランジスタのゲート電極をイニシャル電圧に設定するためのリセットトランジスタとを有する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)