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Machine translation
1. (WO2013157079) CIRCUIT SUBSTRATE AND CIRCUIT SUBSTRATE ON WHICH SEMICONDUCOR DEVICE IS MOUNTED
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2013/157079    International Application No.:    PCT/JP2012/060345
Publication Date: 24.10.2013 International Filing Date: 17.04.2012
IPC:
H01L 23/12 (2006.01), H05K 1/02 (2006.01)
Applicants: RENESAS ELECTRONICS CORPORATION [JP/JP]; 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 2118668 (JP) (For All Designated States Except US).
OTANI, Tomokazu [JP/JP]; (JP) (For US Only).
SANEMITSU, Yoshikado [JP/JP]; (JP) (For US Only).
YAMAMOTO, Yukihiro [JP/JP]; (JP) (For US Only)
Inventors: OTANI, Tomokazu; (JP).
SANEMITSU, Yoshikado; (JP).
YAMAMOTO, Yukihiro; (JP)
Agent: Fukami Patent Office, p.c.; Nakanoshima Central Tower, 2-7, Nakanoshima 2-chome, Kita-ku, Osaka-shi, Osaka 5300005 (JP)
Priority Data:
Title (EN) CIRCUIT SUBSTRATE AND CIRCUIT SUBSTRATE ON WHICH SEMICONDUCOR DEVICE IS MOUNTED
(FR) SUBSTRAT DE CIRCUIT, ET SUBSTRAT DE CIRCUIT SUR LEQUEL EST MONTÉ UN DISPOSITIF À SEMI-CONDUCTEURS
(JA) 回路基板および半導体装置実装回路基板
Abstract: front page image
(EN)Multiple lands (LA) are arranged at each of a group of intersections (IPA1), which excludes one group of intersections (IPA2) of the multiple intersections (IPA) in a virtual grid in the front surface (FS) of a base material (BM). Multiple hole connection parts (HC) are formed so as to connect the front surface (FS) and the back surface (BS) of the base material (BM) within a region (RA1) that includes the one group of intersections (IPA2). Of the multiple hole connection parts (HC), the hole connection parts (HC) which are adjacent to each other are aligned in a different direction than the vertical lines (L1A) and/or the horizontal lines (L2A) that intersect each other in the virtual grid on the front surface (FS).
(FR)De multiples pastilles (LA) sont agencées au niveau de chaque intersection d'un groupe d'intersections (IPA1), qui exclut un groupe d'intersections (IPA2) des intersections multiples (IPA) dans une grille virtuelle dans la surface avant (FS) d'un matériau de base (BM). De multiples parties de connexion de trou (HC) sont formées de façon à connecter la surface avant (FS) et la surface arrière (BS) du matériau de base (BM) dans une région (RA1) qui inclut ledit groupe d'intersections (IPA2). Parmi les multiples parties de connexion de trou (HC), les parties de connexion de trou (HC) qui sont adjacentes les unes aux autres sont alignées dans une direction différente de celle des lignes verticales (L1A) et/ou des lignes horizontales (L2A) qui se recoupent les unes avec les autres dans la grille virtuelle sur la surface avant (FS).
(JA) 複数のランド(LA)が基材(BM)の表面(FS)において仮想の格子の複数の交点(IPA)のうち一の群の交点(IPA2)を除いて他の群の交点(IPA1)の各々に配置されている。複数のホール接続部(HC)は、一の群の交点(IPA2)を含む領域(R1A)内において基材(BM)の表面(FS)と裏面(BS)とを貫通するように形成されている。複数のホール接続部(HC)のうち互いに隣り合うホール接続部(HC)の各々は、表面(FS)において仮想の格子の互いに交差する縦線(L1A)および横線(L2A)の少なくともいずれかと異なる方向に並んでいる。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)