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1. (WO2013157047) TRANSISTOR USING NITRIDE SEMICONDUCTOR AND METHOD FOR MANUFACTURING SAME
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2013/157047 International Application No.: PCT/JP2012/002749
Publication Date: 24.10.2013 International Filing Date: 20.04.2012
IPC:
H01L 21/338 (2006.01) ,H01L 29/778 (2006.01) ,H01L 29/812 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
338
with a Schottky gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
778
with two-dimensional charge carrier gas channel, e.g. HEMT
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
80
with field effect produced by a PN or other rectifying junction gate
812
with a Schottky gate
Applicants: OISHI, Toshiyuki; JP (UsOnly)
YAMAGUCHI, Yutaro; JP (UsOnly)
OTSUKA, Hiroshi; JP (UsOnly)
YAMANAKA, Koji; JP (UsOnly)
NAKAYAMA, Masatoshi; JP (UsOnly)
Mitsubishi Electric Corporation[JP/JP]; 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008310, JP (AllExceptUS)
Inventors: OISHI, Toshiyuki; JP
YAMAGUCHI, Yutaro; JP
OTSUKA, Hiroshi; JP
YAMANAKA, Koji; JP
NAKAYAMA, Masatoshi; JP
Agent: TAZAWA, Hideaki; Akasaka Sanno Center Bldg. 5F, 12-4, Nagata-cho 2-chome, Chiyoda-ku, Tokyo 1000014, JP
Priority Data:
Title (EN) TRANSISTOR USING NITRIDE SEMICONDUCTOR AND METHOD FOR MANUFACTURING SAME
(FR) TRANSISTOR UTILISANT UN SEMI-CONDUCTEUR AU NITRURE ET SON PROCÉDÉ DE FABRICATION
(JA) 窒化物半導体を用いたトランジスタおよびその製造方法
Abstract:
(EN) A transistor, wherein a cap layer, said cap layer being configured from an SiN cap layer (5) containing Si and N that is formed on a barrier layer (4) and an AlGaN layer (6) that has a composition ratio of Al larger than 0 and not larger than 1, is provided at least on the side surface of a gate electrode (9) on the side of a drain electrode (8).
(FR) La présente invention concerne un transistor comportant une couche de coiffe, ladite couche de coiffe étant configurée à partir d'une couche de coiffe SiN (5) contenant Si et N qui est formée sur une couche barrière (4) et une couche AlGan (6) qui comprend un rapport de composition de Al compris entre 0 et 1, est prévue au moins sur la surface latérale d'une électrode de grille (9) sur le côté d'une électrode de drain (8).
(JA)  バリア層4の上部に形成したSiとNを含むSiNキャップ層5とAl組成が0より大きく1以下であるAlGaN層6とから構成したキャップ層をゲート電極9の少なくともドレイン電極8側の側面に設けた。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)