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1. (WO2013156568) CIRCUIT ARRANGEMENT FOR THERMALLY CONDUCTIVE CHIP ASSEMBLY AND PRODUCTION METHOD
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2013/156568 International Application No.: PCT/EP2013/058094
Publication Date: 24.10.2013 International Filing Date: 18.04.2013
IPC:
H01L 21/58 (2006.01) ,H01L 23/367 (2006.01) ,H01L 23/36 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
58
Mounting semiconductor devices on supports
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
36
Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
367
Cooling facilitated by shape of device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
36
Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
Applicants:
ROHDE & SCHWARZ GMBH & CO. KG [DE/DE]; Mühldorfstr. 15 81671 München, DE
Inventors:
ZIEGLER, Robert; DE
Agent:
KÖRFER, Thomas; Mitscherlich & Partner Patent- und Rechtsanwälte Sonnenstr. 33 80331 München, DE
Priority Data:
10 2012 206 362.518.04.2012DE
13/466,31708.05.2012US
Title (EN) CIRCUIT ARRANGEMENT FOR THERMALLY CONDUCTIVE CHIP ASSEMBLY AND PRODUCTION METHOD
(FR) ENSEMBLE CIRCUIT POUR LE MONTAGE DE PUCES THERMIQUEMENT CONDUCTEUR ET PROCÉDÉ DE FABRICATION
(DE) SCHALTUNGSANORDNUNG ZUR THERMISCH LEITFÄHIGEN CHIPMONTAGE UND HERSTELLUNGSVERFAHREN
Abstract:
(EN) A circuit arrangement according to the invention has a substrate (10), a connecting element (18) and a chip (16). The substrate (10) has an at least partial metallisation (11) on the surface thereof. The connecting element (18) is applied to the metallisation (11). The chip (16) is applied to the connecting element (18). The connecting element (18) has an electrically non-conductive glass layer (14) which is applied directly to the metallisation (11), and an adhesive layer (15) between the chip (16) and the glass layer (14).
(FR) L'invention concerne un ensemble circuit comprenant un substrat (10), un élément de connexion (18) et une puce (16). Le substrat (10) comporte sur sa surface une métallisation (11) au moins partielle. L'élément de connexion (18) est appliqué sur la métallisation (11). La puce (16) est appliquée sur l'élément de connexion (18). L'élément de connexion (18) comporte une couche de verre (14) électriquement non conductrice, qui est appliquée directement sur la métallisation (11), et une couche de colle (15) entre la puce (16) et la couche de verre (14).
(DE) Eine erfindungsgemäße Schaltungsanordnung weist ein Substrat (10), ein Verbindungselement (18) und einen Chip (16) auf. Das Substrat (10) weist auf seiner Oberfläche eine zumindest teilweise Metallisierung (11) auf. Das Verbindungselement (18) ist auf der Metallisierung (11) aufgebracht. Der Chip (16) ist auf dem Verbindungselement (18) aufgebracht. Das Verbindungselement (18) weist eine elektrisch nichtleitende Glasschicht (14), welche direkt auf der Metallisierung (11) aufgebracht ist, und eine Kleberschicht (15) zwischen dem Chip (16) und der Glasschicht (14) auf.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: German (DE)
Filing Language: German (DE)