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1. (WO2013155740) SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2013/155740 International Application No.: PCT/CN2012/075309
Publication Date: 24.10.2013 International Filing Date: 10.05.2012
IPC:
H01L 29/06 (2006.01) ,H01L 21/336 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
Applicants: YIN, Haizhou[CN/US]; US (UsOnly)
ZHU, Huilong[US/US]; US (UsOnly)
LUO, Zhijiong[US/US]; US (UsOnly)
INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES[CN/CN]; No.3 Beitucheng West Road, Chaoyang District Beijing 100029, CN (AllExceptUS)
Inventors: YIN, Haizhou; US
ZHU, Huilong; US
LUO, Zhijiong; US
Agent: HANHOW INTELLECTUAL PROPERTY PARTNERS; ZHU Haibo W1-1111,F/11 Oriental plaza, No.1 East Chang An Avenue, Dongcheng District Beijing 100738, CN
Priority Data:
201210117033.519.04.2012CN
Title (EN) SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR
(FR) STRUCTURE SEMI-CONDUCTRICE ET PROCÉDÉ DE FABRICATION DE CELLE-CI
(ZH) 一种半导体结构及其制造方法
Abstract:
(EN) A semiconductor structure comprises: a semiconductor body (120), wherein the semiconductor body (120) is located on an insulating layer (110), and the insulating layer (110) is located on a semiconductor substrate (100); source and drain regions (140) which are connected to two opposite first side surfaces (126) of the semiconductor body (120); gate electrodes (160) which are located on two opposite second side surfaces (128) of the semiconductor body (120); an insulating plug (124) which is located on the insulating layer (110) and embedded in the semiconductor body (120); and an epitaxial layer (180) which is sandwiched between the insulating plug (124) and the semiconductor body (120). A manufacturing method for a semiconductor structure comprises: forming an insulating layer (110) on a semiconductor substrate (100); forming a semiconductor body (120) on the insulating layer (110); forming a cavity in the semiconductor body (120), the cavity exposing the semiconductor substrate (100); forming an epitaxial layer (180) in the cavity by selective epitaxial growth; and forming an insulating plug (124) in the cavity. By forming a super-steep retrograde well, it is advantageously possible to reduce the short-channel effect.
(FR) L'invention concerne un structure semi-conductrice comprenant : un corps semi-conducteur (120), le corps semi-conducteur (120) étant situé sur une couche isolante (110) et la couche isolante (110) étant placée sur un substrat semi-conducteur (100); des régions de source et de drain (140) qui sont connectées à deux surfaces opposées d'un premier côté (126) du corps semi-conducteur (120); des électrodes de grille (160) qui sont situées sur deux surfaces opposées d'un second côté (128) du corps semi-conducteur (120); une fiche isolante (124) qui est située sur la couche isolante (110) et est intégrée dans le corps semi-conducteur (120); et une couche épitaxiale (180) qui est prise en sandwich entre la prise isolante (124) et le corps semi-conducteur (120). Un procédé de fabrication d'une structure semi-conductrice comprend : la formation d'une couche isolante (110) sur un substrat semi-conducteur (100); la formation d'un corps semi-conducteur (120) sur la couche isolante (110); la formation d'une cavité dans le corps semi-conducteur (120), la cavité exposant le substrat semi-conducteur (100); la formation d'une couche épitaxiale (180) dans la cavité par une croissance épitaxiale sélective; et la formation d'une prise isolante (124) dans la cavité. Par formation d'un puits rétrograde extrêmement incliné, il est avantageusement possible de réduire l'effet de canal court.
(ZH) 一种半导体结构,包括,半导体基体(120),所述半导体基体(120)位于绝缘层(110)上,且所述绝缘层(110)位于半导体衬底(100)上;源漏区(140),其接于所述半导体基体(120)的两个相对的第一侧面(126);栅极(160),其位于所述半导体基体(120)的两个相对的第二侧面上(128);绝缘塞(124),位于所述绝缘层(110)上并嵌于所述半导体基体(120)中;外延层(180),夹于所述绝缘塞(124)和所述半导体基体(120)之间。一种半导体结构的形成方法,包括:在半导体衬底(100)上形成绝缘层(110);在绝缘层(110)上形成半导体基体(120);在所述半导体基体(120)内形成空腔,所述空腔暴露所述半导体衬底(100);在所述空腔中选择性外延形成外延层(180);在所述空腔中形成绝缘塞(124)。通过形成超陡的倒掺杂阱,利于减小短沟道效应。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)