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1. (WO2013155329) FABRICATING 3D NON-VOLATILE STORAGE WITH ADDITIONAL WORD LINE SELECT GATES
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2013/155329 International Application No.: PCT/US2013/036213
Publication Date: 17.10.2013 International Filing Date: 11.04.2013
IPC:
H01L 29/66 (2006.01) ,H01L 29/786 (2006.01) ,H01L 27/115 (2006.01) ,H01L 21/265 (2006.01) ,G11C 16/08 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
112
Read-only memory structures
115
Electrically programmable read-only memories
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
26
Bombardment with wave or particle radiation
263
with high-energy radiation
265
producing ion implantation
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
06
Auxiliary circuits, e.g. for writing into memory
08
Address circuits; Decoders; Word-line control circuits
Applicants:
RABKIN, Peter [US/US]; US (US)
HIGASHITANI, Masaaki [US/US]; US (US)
SANDISK TECHNOLOGIES, INC. [US/US]; Two Legacy Town Center 6900 North Dallas Parkway Plano, TX 75024, US (AllExceptUS)
Inventors:
RABKIN, Peter; US
HIGASHITANI, Masaaki; US
Agent:
MAGEN, Burt; Vierra Magen Marcus LLP 575 Market Street, Suite 3750 San Francisco, CA 94105, US
Priority Data:
13/733,03902.01.2013US
61/624,10213.04.2012US
Title (EN) FABRICATING 3D NON-VOLATILE STORAGE WITH ADDITIONAL WORD LINE SELECT GATES
(FR) FABRICATION DE MÉMOIRE NON VOLATILE 3D À GRILLES DE SÉLECTION DE LIGNE DE MOT SUPPLÉMENTAIRES
Abstract:
(EN) Disclosed herein are techniques for fabricating a 3D stacked memory device having word line (WL) select gates (229). The bodies (231) of the WL select gates may be formed from the same material (e.g., highly doped polysilicon) that the word lines are formed of. Desired doping profiles in a body of a WL select gate may be achieved by various techniques such as counter-doping. The WL select gates may include TFTs that are formed by etching holes in the layer in which word lines are formed. Gate electrodes (404) and gate dielectrics (402) may be formed in the holes. Bodies may be formed in the polysilicon outside of the holes.
(FR) L'invention porte sur des techniques pour fabriquer un dispositif de mémoire empilé 3D comportant des grilles de sélection de ligne de mot (WL) (229). Les corps (231) des grilles de sélection de WL peuvent être faits du même matériau (par exemple, du polysilicium fortement dopé) que celui dont sont faites les lignes de mot. Des profils de dopage souhaités dans un corps d'une grille de sélection de WL peuvent être obtenus par diverses techniques telles qu'un contre-dopage. Les grilles de sélection de WL peuvent comporter des transistors en couches minces (TFT) qui sont formés par gravure de trous dans la couche dans laquelle les lignes de mot sont formées. Des électrodes de grille (404) et des diélectriques de grille (402) peuvent être formés dans les trous. Des corps peuvent être formés dans le polysilicium à l'extérieur des trous.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)