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Pub. No.: WO/2013/154144 International Application No.: PCT/JP2013/060888
Publication Date: 17.10.2013 International Filing Date: 11.04.2013
IPC:
G01F 1/68 (2006.01) ,H01L 21/56 (2006.01)
G PHYSICS
01
MEASURING; TESTING
F
MEASURING VOLUME, VOLUME FLOW, MASS FLOW, OR LIQUID LEVEL; METERING BY VOLUME
1
Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through the meter in a continuous flow
68
by using thermal effects
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
56
Encapsulations, e.g. encapsulating layers, coatings
Applicants: HITACHI AUTOMOTIVE SYSTEMS, LTD.[JP/JP]; 2520, Takaba, Hitachinaka-shi, Ibaraki 3128503, JP
Inventors: KONO, Tsutomu; JP
HANZAWA, Keiji; JP
TOKUYASU, Noboru; JP
TASHIRO, Shinobu; JP
Agent: TSUTSUI, Yamato; Tsutsui & Associates, 3F, Shinjuku Gyoen Bldg., 3-10, Shinjuku 2-chome, Shinjuku-ku, Tokyo 1600022, JP
Priority Data:
2012-09128812.04.2012JP
Title (EN) FLOW RATE SENSOR AND METHOD FOR MAKING SAME
(FR) CAPTEUR DE DÉBIT ET SON PROCÉDÉ DE FABRICATION
(JA) 流量センサおよびその製造方法
Abstract:
(EN) Provided is a technique for suppressing variations in performance of flow rate sensors and improving the performances thereof. For example, in any given cross-section parallel to the traveling direction of a gas flowing over an exposed flow-rate detecting unit (FDU) formed on a semiconductor chip (CHP1), ejection pins (EJPN), which do not overlap the semiconductor chip (CHP1) located in the vicinity of the center but are located in respective areas outside the semiconductor chip (CHP1), are pushed up from a bottom mold (BM), thereby spacing a sealer from the bottom mold (BM). In this way, according to this embodiment (1) of the invention, the deformation imparted to the sealer during the spacing of the sealer from the bottom mold can be reduced as compared with a case of spacing of the sealer from the bottom mold (BM) with the ejection pins (EJPN) located in respective areas overlapping the semiconductor chip (CHP1).
(FR) L'invention concerne une technique permettant de supprimer les variations de performance des capteurs de débit et d'améliorer leurs performances. Par exemple, dans toute section transversale donnée parallèle à la direction de déplacement d'un gaz s'écoulant au-dessus d'une unité de détection de débit exposée (FDU) formée sur une puce de semiconducteur (CHP1), des broches d'éjection (EJPN), qui ne chevauchent pas la puce de semiconducteur (CHP1) située à proximité du centre mais se trouvent dans des zones respectives à l'extérieur de la puce de semiconducteur (CHP1), sont poussées vers le haut à partir d'un moule inférieur (BM), ce qui écarte un agent d'étanchéité du moule inférieur (BM). De cette manière, selon ce mode de réalisation (1) de l'invention, la déformation imprimée à l'agent d'étanchéité lorsqu'il est écarté du moule inférieur peut être réduite par comparaison au cas de figure dans lequel l'agent d'étanchéité est écarté du moule inférieur (BM) et les broches d'éjection (EJPN) se situent dans des zones respectives chevauchant la puce de semiconducteur (CHP1).
(JA)  流量センサごとの性能バラツキを抑制して性能向上を図ることができる技術を提供する。例えば、半導体チップCHP1に形成された露出している流量検出部FDU上を流れる気体の進行方向と並行する任意断面において、中央部近傍に配置されている半導体チップCHP1と重ならずに半導体チップCHP1の外側領域に配置された突き出しピンEJPNを下金型BMから突き上げることにより、封止体を下金型BMから離型している。これにより、本実施の形態1によれば、半導体チップCHP1と重なる領域に突き出しピンEJPNを配置して封止体の下金型BMからの離型を行なう場合に比べて、離型の際に封止体に加わる変形を小さくすることができる。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)