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1. (WO2013153894) CASCODE AMPLIFIER AND AMPLIFIER CIRCUIT
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2013/153894 International Application No.: PCT/JP2013/056794
Publication Date: 17.10.2013 International Filing Date: 12.03.2013
IPC:
H03F 1/22 (2006.01) ,H03F 3/193 (2006.01) ,H03F 3/68 (2006.01)
Applicants: NITTA, Naoko; JP (US)
KATO, Katsuya; JP (US)
MUKAI, Kenji; JP (US)
HORIGUCHI, Kenichi; JP (US)
HIEDA, Morishige; JP (US)
MORI, Kazutomi; JP (US)
YAMAMOTO, Kazuya; JP (US)
MITSUBISHI ELECTRIC CORPORATION[JP/JP]; 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008310, JP (AllExceptUS)
Inventors: NITTA, Naoko; JP
KATO, Katsuya; JP
MUKAI, Kenji; JP
HORIGUCHI, Kenichi; JP
HIEDA, Morishige; JP
MORI, Kazutomi; JP
YAMAMOTO, Kazuya; JP
Agent: TAZAWA, Hideaki; Akasaka Sanno Center Bldg. 5F, 12-4, Nagata-cho 2-chome, Chiyoda-ku, Tokyo 1000014, JP
Priority Data:
2012-08847909.04.2012JP
Title (EN) CASCODE AMPLIFIER AND AMPLIFIER CIRCUIT
(FR) CIRCUIT AMPLIFICATEUR ET AMPLIFICATEUR EN MONTAGE CASCODE
(JA) カスコード増幅器及び増幅回路
Abstract: front page image
(EN) Provided is a cascode amplifier in which the withstand voltage between the terminals of FET 2 (withstand voltage B) is greater than the withstand voltage between the terminals of FET 1 (withstand voltage A) and the gate width of FET 1 (Wg 1) is smaller than the gate width of FET 2 (Wg 2). This configuration makes it possible to increase the gain while maintaining high output power. Additionally, since the gate width of FET 1 (Wg 1) that is connected to an input terminal (3) is small, the size of the cascode amplifier can be reduced.
(FR) L'invention concerne un amplificateur en montage cascode dans lequel la tension de claquage entre les bornes du transistor à effet de champ (FET) 2 (tension de claquage B) est supérieure à la tension de claquage entre les bornes du FET 1 (tension de claquage A) et la largeur de grille du FET 1 (Wg 1) est inférieure à la largeur de grille du FET 2 (Wg 2). Cette configuration rend possible l'augmentation du gain tout en maintenant une puissance de sortie élevée. De plus, étant donné que la largeur de grille du FET 1 (Wg 1) qui est connectée à une borne d'entrée (3) est petite, la taille de l'amplificateur en montage cascode peut être réduite.
(JA)  FET2の端子間耐圧(耐圧B)が、FET1の端子間耐圧(耐圧A)より高く、FET1のゲート幅(Wg1)が、FET2のゲート幅(Wg2)より小さく構成されている。これにより、高出力電力を確保しながら、利得を高めることができる。また、入力端子3に接続されるFET1のゲート幅(Wg1)が小さいため、カスコード増幅器の小型化を図ることができる。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)